TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 200

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EBC
9.2.8.2.
When in the ACK*/Ready Static mode, the ACK*/Ready signal is always an input signal. When in the ACK*/Ready Dynamic
mode, the ACK*/Ready signal is an input signal when in the External ACK mode or the Ready mode, but is an output signal
in all other modes.
During External ACK mode or Ready mode access, the ACK* signal becomes High-Z at the cycle where the CE* signal is
asserted. At the end of the access cycle, the ACK* signal is output (driven) again one clock cycle after the CE* signal is
de-asserted.
9.2.8.3.
When in the Normal mode and Page mode of the ACK*/Ready Dynamic mode, the ACK* signal becomes an output signal
and is asserted for one clock cycle to send notification to the external device of the data Read and data Write timing.
During the Read cycle, the data is latched at the rise of the next clock cycle after when the ACK* signal is asserted.
During the Write cycle, SWE*/BWE* is deasserted at the next clock cycle after when the ACK* signal is deasserted, and the
data is held for one more clock cycle after that.
Rev. 3.1 November 1, 2005
ACK*/READY
SWE*/BWE*
SADB [15:0]
AD [28:6]
SYSCLK
SA [5:0]
output
ACE*
OE*
CE*
ACK*/READY Input/Output Switching Timing
ACK* Output Timing (Normal Mode, Page Mode)
0
1
0
2
Single Read Cycle
Figure 9-8 ACK* Output Timing (Single Read/Write Cycle)
3
1
ACK* Output Timing (Normal Mode, Page Mode )
4
2
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
5
1
6
7
9-10
8
9
10
11
12
Single Write Cycle
13
14
0
EBCCRn.PWT:WT=2
EBCCRn.SHWT=0
Toshiba RISC Processor
15
1
16
2
1
17
2 clock
18
19
TX4939
Rev 2.13
9
9