TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 471

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

ATA100
17.3.3.14. Command/Status Register ATA Shadow (007h)
You can use this register when reading Status Register or writing to the device Command Register of the device. Access to
the device ATA Register begins when TX4939 accesses this register.
The following signals correspond to the following register addresses:
17.3.3.15. Alternate Status Register ATA Shadow (402h)
You can use this register when reading Alternate Status Register or writing to Device Control Register of the device. Access
to the device ATA Register begins when TX4939 accesses this register.
The following signals correspond to the following register addresses: CS0N → 1, CS1N → 0, HA[2:0] → 6h.
17.3.3.16. PIO Access Address Register (C88h)
Setting this register makes it possible to forcibly set values such as the address that is provided to the device. This setting
becomes valid when not accessing the device ATA registers nor performing data transfer. During data transfer, the values in
the following table are automatically used.
Rev. 3.1 November 1, 2005
BIT
Bit[4]:
Bit[3]:
Bit[2:0]:
Bit 15
Bit 7
Bit 7
Bit 7
R/W
R/W
0
0
0
0
-
-
NAME
CS1N
CS0N
HA[2:0]
Not Used
Bit 14
Bit 6
Bit 6
Bit 6
R/W
R/W
0
0
0
0
-
-
CS0N → 0, CS1N → 1, HA[2:0] → 7h.
Figure 17-19 Command/Status Register ATA Shadow
Figure 17-20 Alternate Status Register ATA Shadow
Bit 13
Bit 5
Bit 5
Bit 5
R/W
R/W
Figure 17-21 PIO Access Address Register
0
0
0
0
-
-
Table 17-3 PIO Access Address Register
Description
This bit determines bit 1 of Chip Select.
This bit determined bit 0 of Chip Select.
This field determines the ATA address Bus.
Alternate Status/Device Control Register
Transfer Mode
PIO
Multiword DMA
Ultra DMA
Command/Status Register
Bit 12
CS1N
Bit 4
Bit 4
Bit 4
R/W
R/W
R/W
0
0
0
1
-
17-17
Not Used
Bit 11
CS0N
Bit 3
Bit 3
Bit 3
R/W
R/W
R/W
0
0
0
1
-
CS0N
0
1
1
Bit 10
Bit 2
Bit 2
Bit 2
R/W
R/W
R/W
0
0
0
0
-
CS1N
1
1
1
Toshiba RISC Processor
HA[2:0]
Bit 1
Bit 1
Bit 9
Bit 1
R/W
R/W
R/W
0
0
0
0
-
HA[2:0]
0
0
0
Bit 0
Bit 0
Bit 8
Bit 0
R/W
R/W
R/W
0
0
0
0
-
TX4939
17
17