TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 310

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.4.1. DMA Master Control Register (DM0MCR, DM1MCR)
Offset address:
Rev. 3.1 November 1, 2005
Bit
63:32
31:28
27:24
23:21
20:14
13:11
10:8
7
Default
Default
Default
Default
Name
Name
Name
Name
Type
Type
Type
Type
Mnemonic
EIS[3:0]
DIS[3:0]
FIFVC
FIFWP
FIFRP
RSFIF
63
47
31
15
FIFVC
DMAC0 0xB150, DMAC1 0xB950
62
46
30
14
EIS[3:0]
0000
R
Field Name
Reserved
Error Interrupt
Status
Normal
Completion
Interrupt Status
Reserved
FIFO Valid Entry
Count
FIFO Write
Pointer
FIFO Read
Pointer
Reset FIFO
61
45
29
13
FIFWP
000
60
44
28
12
R
Figure 14-9 DMA Master Control Register
Table 14-7 DMA Master Control Register
59
43
27
11
Description
Error Interrupt Status [3:0] (Default: 0x0)
These four bits indicate the error interrupt status of each channel. EIS[n]
corresponds to channel n.
1: There is an error interrupt in the corresponding channel.
0: There is no error interrupt in the corresponding channel.
Done Interrupt Status [3:0] (Default: 0x0)
These four bits indicate the transfer completion (transfer complete or chain
ended) interrupt status of each channel. DIS[n] corresponds to channel n.
1: There is a transfer completion interrupt in the corresponding channel.
0: There is no transfer completion interrupt in the corresponding channel.
FIFO Valid Entry Count (Default: 0000000)
These read only bits indicate the byte count of data that were written to
FIFO but not read out from the FIFO.
FIFO Write Pointer (Default: 000)
These read only bits indicate the next write position in FIFO. This is a
diagnostic function.
FIFO Read Pointer (Default: 000)
These read only bits indicate the next read position in FIFO. This is a
diagnostic function.
Reset FIFO (Default: 0)
This bit is used for resetting FIFO. When this bit is set to “1”, the FIFO read
pointer, FIFO write pointer and FIFO valid entry count are initialized to “0”.
If an error occurs during DMA transfer, use this bit when data remains in the
FIFO (when the FIFO Valid entry Count Field is not “0”) to initialize the
FIFO.
58
42
26
10
DIS[3:0]
0000
R
FIFRP
000
57
41
25
R
9
This register controls the entire DMA Controller.
14-22
RESERVED
RESERVED
56
40
24
8
RSFIF
R/W
55
39
23
7
0
Reserved
54
38
22
6
FIFUM[3:0]
53
37
21
5
0000
R/W
52
36
20
4
Toshiba RISC Processor
51
35
19
3
FIFVC
00000
Rsvd RRPT
50
34
18
R
2
R/W
49
33
17
1
0
R/W
⎯
R
R
⎯
R
R
R
R/W
TX4939
MSTE
R/W
48
32
16
N
0
0
14
14