TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 465

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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ATA100
17.3.2.6. Transfer Word Count 2 Register (C0Ah):
This register sets the transfer word count in ATA100 Core for a slave device. The register description is the same as the
transfer word count register in ATA100 Core below.
This register sets the transferred word count for each sector. When the size of 1 sector transferred to the device is 512 bytes,
you do not need to change this register from its default state. Set bits [10:8] to the following values: 001 → 512 bytes; 010
→ 1024 bytes; 100 → 2048 bytes.
Calculate the amount of data transferred by a single command as shown below.
When any sector data transfer starts, the transfer word number for each sector to be performed is set in this register and this
number is decremented when each transfer is performed.
Rev. 3.1 November 1, 2005
Note 1)
Bit 15
Bit 7
R/W
R/W
Total Transfer Word Count = Transfer Word Count [15:0] × Sector Count [15:0]
0
0
You must set “00h” to the lower order of the Transfer Word Count when setting a value other
than 1 to the Sector Count.
Bit 14
Bit 6
R/W
R/W
0
0
Bit 13
Bit 5
R/W
R/W
Figure 17-8 Transfer Word Count 2 Register
0
0
Transfer Word Count[15:8]
Transfer Word Count[7:0]
Bit 12
Bit 4
R/W
R/W
0
0
17-11
Bit 11
Bit 3
R/W
R/W
0
0
Bit 10
Bit 2
R/W
R/W
0
0
Toshiba RISC Processor
Bit 9
Bit 1
R/W
R/W
0
0
Bit 8
Bit 0
R/W
R/W
1
0
TX4939
17
17

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