TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 117

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Address
6.4. PCI Address Space Mapping
This section describes new feature that is introduced TX4939 PCI Controller. It is related memory mapping from PCI
Memory Space to GBUS Memory Space. This mapping will be used when any PCI Master Device (external devices)
access any memory device attached GBUS (DDR Memory is an example) through PGB (PCI to GBUS Bridge).
TX4939 has three windows for this mapping. Three control registers are provided to define the mapping windows as same
as TMPR4938XB, however each window size is now programmable. (Note: TMPR4938XB has three windows but each
window has fixed size, such as 512 MB (Window#0), 16 MB (Window #1), and 1 MB (Window #2).
6.4.1. P2G Memory Space (n) PCI Lower Base Address Register (n=0,1,2)
These registers are corresponding to the PCI-GBUS Window #n. Those registers are P2GM0PLBASE, P2GM1PLBASE,
P2GM2PLBASE,
Rev. 3.1 November 1, 2005
31:20
19:16
15:13
12:4
3
2:1
0
Bit
R/W
R/O
31
15
0
1
MSS [31:29]
R/W
BA [31:20]
MSS [31:29]
MSS [28:20]
PF
TYPE
MSI
R/O
30
14
Mnemonic
0
1
R/W
R/O
29
13
0
1
R/W
R/W
28
12
0
0
Base Address
RESERVED
Size (Maximum)
Size
Prefetchable
Type
Memory Space
Figure 6-6 P2G Memory Space (n) PCI Lower Address Register
Field Name
Table 6-4 P2G Memory Space (n) PCI Lower Address Register
R/W
R/W
27
11
0
0
R/W
R/W
BA [31:20]
26
10
0
0
R/W
R/W
25
Base Address (Default=0x000)
Sets the lower address of the PCI base address in Target Access
Memory Space n. The size of Memory Space is defined by the
value of MSS [23:20].
Effective Base Address (EBA) is given by following formula.
EBA [31:20] = BA[31:20] & MSS [31:20] ( bitwise AND )
Memory Space Size (Default=0x000, 512 MB)
See
Table 6-5 for other corresponding.
Prefetchable
1: Indicates that memory is prefetchable.
0: Indicates that memory is not prefetchable.
Type (Default: 00)
00: Indicates that an address is within a 32-bit address region
Memory Space Indicator (Fixed Value: 0)
0: Indicates that this Base Address Register is for use by the PCI
Memory Space
Memory Space Size (Maximum, Default=3'b111, 512 MB).
0
9
0
MSS [28:20]
R/W
R/W
24
0
8
0
R/W
R/W
23
0
7
0
6-7
R/W
R/W
22
0
6
0
Description
R/W
R/W
21
0
5
0
R/W
R/W
20
4
0
0
R/W
R/O
PF
19
0
3
1
RESERVED
R/O
R/O
18
0
2
0
Toshiba RISC Processor
TYPE
R/O
R/O
17
0
1
0
MSI
R/O
R/O
16
0
0
0
0x000
4'b0000
3'b111
0x000
1
0
0
Default
: Default
: Default
: R/W
: R/W
TX4939
R/W
R/O
R/O
R/W
R/W
R/O
R/O
R/W
6
6