TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 572
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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SIO
Table 19-2 gives example divide value settings and percentage error from targeted baud rates when IMBUSCLK is used to
generate SIOCLK (Figure 19-3). Exact target baud rates cannot be achieved when using IMBUSCLK to generate SIOCLK.
Table 19-3 gives example divide values and jitter per bit time for targeted baud rates when SCLK0 is used to generate
SIOCLK (Figure 19-3). Exact target baud rates are achieved when using SCLK0 to generate SIOCLK. However please
note that SCLK0 inherently has jitter due to the process in which it is generated. SCLK0 (baud rate clock) generation
information can be obtained from Chapter 5. Clock Generators.
Rev. 3.1 November 1, 2005
Table 19-2 Example Divide Value Settings when using IMBUSCLK (and error [%] from target baud rate value)
Note 1:
Note 2:
SCLK0 = 14.7456
(Note 1)
IMBUSCLK = 100
(GBUSCLK=200)
(GBUSCLK=150)
IMBUSCLK = 75
Table 19-3 Example Divide Value Settings when using SCLK0 (and jitter value per bit time [%])
Fc [MHz]
fc [MHz]
SCLK0 is not generated by default. MCLKCTL:BDE needs to be set for SCLK0
generation. SCLK0 (baud rate clock) generation information can be obtained from
Chapter 5. Clock Generators.
The baud rate generator circuit (Figure 19-3) is bypassed and SIOCLK is sourced by
SCLK0 when SILCR.SCS is set to 3’b010.
Target
230400
460800
921600
115200
bps
14400
28800
57600
Target
1200
2400
4800
9600
230400
460800
921600
230400
460800
921600
115200
115200
Bps
300
600
14400
28800
57600
14400
28800
57600
1200
2400
4800
9600
1200
2400
4800
9600
300
600
300
600
generator (Note 2)
Bypass baud rate
Note 2 (0.1600%)
163 ( -0.147 %)
41 ( -0.756 %)
217(-0.006%)
81 ( 0.469 %)
20 ( 1.725 %)
10 ( 1.725 %)
109(0.452%)
54(-0.469%)
27(-0.469%)
5 ( 1.725 %)
14(3.119%)
2
7(3.119%)
Prescalar Value (SIBGR.BCLK) and Divide Value (SIBGR.BRD)
Prescalar Value (SIBGR.BCLK) and Divide Value (SIBGR.BRD)
19-6
192(0.0004%)
96(0.0008%)
48(0.0017%)
32(0.0025%)
16(0.0050%)
8(0.0100%)
4(0.0200%)
2(0.0400%)
1(0.0800%)
2
244 ( 0.058 %)
122 ( 0.058 %)
41 ( -0.756 %)
163( 0.147%)
61 ( 0.058 %)
81(-0.469%)
54(-0.469%)
27(-0.469%)
8
192(0.0001%)
96(0.0002%)
48(0.0004%)
24(0.0008%)
12(0.0017%)
8(0.0025%)
4(0.0050%)
2(0.0100%)
1(0.0200%)
8
244 ( 0.058 %)
122 ( 0.058 %)
163( 0.147%)
61 ( 0.058 %)
81(-0.469%)
41( 0.756%)
32
96(0.0001%)
48(0.0001%)
24(0.0002%)
12(0.0004%)
Toshiba RISC Processor
6(0.0008%)
3(0.0017%)
2(0.0025%)
1(0.0050%)
32
122 ( 0.058 %)
163( 0.147%)
61 ( 0.058 %)
81(-0.469%)
41( 0.756%)
128
24(0.0001%)
12(0.0001%)
6(0.0002%)
3(0.0004%)
128
TX4939
19
19
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