TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 152

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Configuration
Rev. 3.1 November 1, 2005
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
Bit
PCICKD
I2SCKD
TM0CKD
TM1CKD
TM2CKD
SIO0CKD
CYPCKD
IOSRST
SYSRST
TM5RST
TM4RST
TM3RST
CIRRST
SIO3RST
SIO2RST
SIO1RST
VPCRST
EPCIRST
⎯
ETH1RST
ATA1RST
BROMRST
NDCRST
Mnemonic
PCIC Clock
Disable
I2S Clock
Disable
Timer 0 Clock
Disable
Timer 1 Clock
Disable
Timer 2 Clock
Disable
SIO0 Clock
Disable
CYP Clock
Disable
IOSRST
Reset
SYSRST
Reset
TMR5 Reset
TMR4 Reset
TMR3 Reset
CIR Reset
SIO3 Reset
SIO2 Reset
SIO1 Reset
VPC Reset
EPCIRST
Reset
Reserved
ETH1 Reset
ATA1 Reset
BROM Reset
NDC Reset
Field Name
Controls clock pulses for the PCI controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the I2S controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the TMR0 controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the TMR1 controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the TMR2 controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the SIO0 controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Controls clock pulses for the Cipher controller.
0 = Supply clock pulses.
1 = Do not supply clock pulses.
Resets IO signal IOSRST_.
0 = Normal state
1 = Reset
Resets IO signal SYSRST_.
0 = Normal state
1 = Reset
Resets the TMR5 controller.
0 = Normal state
1 = Reset
Resets the TMR4 controller.
0 = Normal state
1 = Reset
Resets the TMR3 controller.
0 = Normal state
1 = Reset
Resets the CIR controller.
0 = Normal state
1 = Reset
Resets the SIO3 controller.
0 = Normal state
1 = Reset
Resets the SIO2 controller.
0 = Normal state
1 = Reset
Resets the SIO1 controller.
0 = Normal state
1 = Reset
Resets the VPC controller.
0 = Normal state
1 = Reset
Resets IO signal PCIRST_.
0 = Normal state
1 = Reset
⎯
Resets the Ethernet MAC 1 controller.
0 = Normal state
1 = Reset
Resets the ATA1 controller.
0 = Normal state
1 = Reset
Resets the BROM controller.
0 = Normal state
1 = Reset
Resets the NAND Flash controller.
0 = Normal state
1 = Reset
Table 7-6 Clock Control Register
7-14
Description
Toshiba RISC Processor
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
⎯
0
0
0
0
Initial
Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
R/W
R/W
R/W
R/W
Read/Write
TX4939
7
7