TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 265

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Video Port
12.3.6.6. Bus Error Address Register (BusErr)
Note:
Rev. 3.1 November 1, 2005
1- Programmer must set TOE bit in the CCFG register to enable timeout interrupts.
2- The VPC actually does not generate any bus errors. So this is not handled under BusError handler in
3- Enable GBINT in VPC CSR. This will cause an INT to be generated for the CPU
4- This is now an INT handler not a BUSERR (Both share the same vector but handled differently)
5- Inside the handler, software must read CSR to clear GBINT
CPU. Instead it is handled under regular interrupts. Care should be observed in this case for EPC
register in COP0
to clear BusErr register.
Bit(s)
63:32
31:2
1
0
–
--
Field
--
--
R/W
RO
RO
RO
RO
Table 12-7 Bus Error Address Register (BusErr)
Default
0
0
0
0
Description
Reserved
G-bus error address[31:2]
Command status during bus error.
0: Write operation
1: Read operation
When set, indicates the address is valid, i.e. Bus Error has been
captured.
12-13
and issue software reset (DMAC reset - RSTD),
Toshiba RISC Processor
0xA068
TX4939
12
12