TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 92

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Boot Configuration
4.2. Boot Configuration Detail
Rev. 3.1 November 1, 2005
Signal
SA[2:0]
SA[4:3]
SA[5]
DMAACK[2]
DMAACK[1:0]
SADB[0]
SADB[1]
SADB[2]
SADB[3]
SADB[4]
~SADB[5]
Description
CPU Clock Setting (MULCLK[2:0 ] ==> ND[4:0]@PLL#2)
SYSCLK Setting
SSCG Control
PCI Host and Satellite selection setting
1: Host
0: Satellite
CPUCLK/GBUSCLK Ratio Setting
PC Trace Configuration
Specifies the function of the BE[1:0]*/BWE[1:0]* pins upon booting.
1 = BWE[1:0]* (Byte Write Enable)
0 = BE[1:0]* (Byte Enable)
Boot ACK* Input : Specifies the access mode for external bus controller channel 0.
1 = Normal mode
0 = External ACK mode
Boot ROM Bus Width. Specifies the data bus width when booting from a memory device
connected to the External bus controller.
TX4939 Endian Mode : Specifies the TX4939 Endian mode.
1 = Big endian
0 = Little Endian
TX49/H4 Internal Timer Interrupt Disable : Specifies whether timer interrupts within the
TX49/H4 core are enabled.
0 = Enable timer interrupts within the TX49/H4 core.
1 = Disable timer interrupts within the TX49/H4 core.
YDIVMODE[2:0] = {DMAACK[1],DMAACK[1:0]}
SA[2:0]
000
001
010
011
100
101
110
111
DMAACK[1:0]
00
01
10
11
SADB [3]
0
1
(YMULCLK[4:0] = ND[4:0])
Table 4-1 Boot Configuration Details
ND[4:0]
01000
01001
01010
01011
01100
01101
01110
00111
YDIVMODE[2:0]
000
001
110
111
Boot ROM Bus Width
16 bit
8 bit
4-2
00 = DIV4 of Gbus clock
01 = DIV3 of Gbus clock
10 = DIV5 of Gbus clock
11 = DIV6 of Gbus clock
1 : Enable
0 : Disabled
PLL#2
600 MHz
666 MHz
733 MHz
800 MHz
Reserved
Reserved
Reserved
533 MHz
1 = PC Trace Enable
0 = PC Trace Disable
CPUCLK/GBUSCLK
(1 / 2.0)
(1 / 3.0)
(1 / 5.0)
(1 / 6.0)
CPU Clock
300 MHz
333 MHz
366 MHz
400 MHz
Reserved
Reserved
Reserved
266 MHz
Toshiba RISC Processor
Corresponding
Register Bit
MULCLK[2:0]
SYSSP[1:0]
SSCG
CCFG_PCIMODE
YDIVMODE[2:0]
CCFG_PTSEL
CCFG_BESEL
CCFG_ACKSEL
CCFG_ROMW
CCFG_ENDIAN
CCFG_TINTDIS
TX4939
4
4