TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 439

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.57. PDMAC Chain Address Register (PDMCA)
Rev. 3.1 November 1, 2005
Bits
63:36
35:3
2:0
Default
Default
Default
Default
NAME
NAME
NAME
NAME
TYPE
TYPE
TYPE
TYPE
Mnemonic
PDMCA
63
47
31
15
62
46
30
14
Field Name
Rsvd
Chain Address
Rsvd
61
45
29
13
60
44
28
12
Figure 16-68 PDMAC Chain Address Register
Table 16-70 PDMAC Chain Address Register
59
43
27
11
Description
PDMAC Chain Address (Default is undefined)
The address of the next PDMAC Data Command Descriptor to be read is
specified by a G-Bus physical address on a 64-bit address boundary. This
register value is held without being affected by a Reset.
0 value judgement is performed when the lower 32 bits of this register are
rewritten. DMA transfer is automatically initiated if the result is not “0”.
RESERVED
58
42
26
10
PDMCA[15:3]
Undefined
R/W
57
41
25
9
16-75
PDMCA[31:16]
RESERVED
Undefined
56
40
24
8
R/W
55
39
23
7
54
38
22
6
53
37
21
5
52
36
20
Toshiba RISC Processor
4
51
35
19
3
PDMCA[35:32]
50
34
18
undefined
2
RESERVED
R/W
49
33
17
1
R/W
⎯
R/W
⎯
TX4939
48
32
16
0
16
16