TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 638
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
Available stocks
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Manufacturer
Quantity
Price
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Part Number:
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Manufacturer:
NSC
Quantity:
872
Company:
Part Number:
TX4939XBG-400
Manufacturer:
TOSHIBA
Quantity:
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Part Number:
TX4939XBG-400
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I2S
23.4.4. I2S Interrupt Control Register (I2SICTRL)
Rev. 3.1 November 1, 2005
R/W/RO
Reset Value
Bit
D31:22
D21
D20
D19
D18
D17
D16
D15:6
D5
D4
D3
D2
D1
D0
Reset Value
R/W/RO
Bit
Bit
RO
0
RO
31
15
0
RO
0
Field Name
---
---
---
---
---
---
---
---
---
---
---
---
---
---
RO
30
14
0
RO
0
RO
29
13
0
RO
0
RO
28
12
0
0
RO
Description
Reserved
Underrun/Overrun Interrupt Mask for Channel 1 i/o mode
When 3 Channel Mode is enable, this bit must set to “1”.
Underrun/Overrun Interrupt Mask for Channel 0 i/o mode and 3
channel output mode
WS1 Error Detect Interrupt Mask
When 3 Channel Mode is enable, this bit must set to “1”.
WS0 Error Detect Interrupt Mask
MCLK1 Error Detect Interrupt Mask
When 3 Channel Mode is enable, this bit must set to “1”.
MCLK0 Error Detect Interrupt Mask
Reserved
Underrun/Overrun Interrupt Status for Channel 1 i/o mode
Write “1” to clear the interrupt
Underrun/Overrun Interrupt Status for Channel 0 i/o and 3 channel
output mode
Write “1” to clear the interrupt
WS1 Error Detect Interrupt Status
Write “1” to clear the interrupt
WS0 Error Detect Interrupt Status
Write “1” to clear the interrupt
MCLK1 Error Detect Interrupt Status
Write “1” to clear the interrupt
MCLK0 Error Detect Interrupt Status
Write “1” to clear the interrupt
RO
27
11
0
RO
0
RO
26
10
0
23-14
0: Normal
1: Mask (default)
0: Normal
1: Mask (default)
0: Normal
1: Mask (default)
0: Normal
1: Mask (default)
0: Normal
1: Interrupt
0: Normal
1: Interrupt
0: Normal
1: Interrupt
RO
0
0: Normal
1: Interrupt
RO
25
0: Normal
1: Interrupt
0: Normal
1: Interrupt
0
9
RO
0
RO
24
0
8
RO
0
RO
23
0
7
RO
0
RO R/W R/W R/W R/W R/W R/W
22
0
6
R/W R/W R/W R/W R/W R/W
0
21
1
5
0
20
1
4
Toshiba RISC Processor
0
19
3
1
0
18
1
2
0xFA08
0
17
1
1
0
16
1
0
TX4939
23
23
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