TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 619

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TX4939XBG-400

Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet

Specifications of TX4939XBG-400

Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456

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I2C
22.3.8. Clock Stretching
Slave devices can use the clock synchronization mechanism to slow down the transfer bit rate. After the master has
driven SCL low, the slave can drive SCL low for the required period and then release it. If the slave’s SCL low period is
greater than the master’s SCL low period, the resulting SCL bus signal low period is stretched, thus inserting wait-states.
22.4. Architecture
The I2C core is built around four primary blocks; the Clock Generator, the Byte Command Controller, the Bit Command
Controller and the DataIO Shift Register.
All other blocks are used for interfacing or for storing temporary values.
Rev. 3.1 November 1, 2005
Interface
IMB
FIFO
9x32
Receive Register
Status Register
Command
Prescale
Transmit
Register
Register
Register
Figure 22-4 Internal structure I2C
22-9
Byte Command
Shift Register
Controller
DataIO
clock generator
Bit Command
Controller
Toshiba RISC Processor
SDA
SCL
TX4939
22
22

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