TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 319

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

DMA
14.4.5. DMA Destination Address Register (DM0DARn, DM1DARn)
Offset Address:
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
Name
Name
Name
Name
Bit
63:36
35:0
Type
Type
Type
Type
Mnemonic
DADDR
63
47
31
15
DMAC0 0xB010 (ch. 0) / 0xB050 (ch. 1) / 0xB090 (ch. 2) / 0xB0D0 (ch. 3)
DMAC1 0xB810 (ch. 0) / 0xB850 (ch. 1) / 0xB890 (ch. 2) / 0xB8D0 (ch. 3)
62
46
30
14
61
45
29
13
Field Name
Reserved
Destination
Address
60
44
28
12
Figure 14-13 DMA Destination Address Register
Table 14-11 DMA Destination Address Register
59
43
27
11
Description
Destination Address (Default: undefined)
This register sets the physical address of the transfer destination during Dual
Address transfer. This register is ignored during Single Address transfer.
Refer to “14.3.8.1 Channel Register Settings During Dual Address Transfer”
for more information.
During Burst transfer, the value changes only by the size of data transferred
during each single bus operation. During Single transfer, the value only
changes by the value specified by the DMA Destination Address Increment
Register (DMDAIRn).
RESERVED
58
42
26
10
57
41
25
9
14-31
DADDR[31:16]
DADDR[15:0]
RESERVED
56
40
24
8
R/W
R/W
⎯
⎯
55
39
23
7
54
38
22
6
53
37
21
5
52
36
20
4
Toshiba RISC Processor
51
35
19
3
DADDR[35:32]
50
34
18
2
R/W
⎯
49
33
17
1
R/W
⎯
R/W
TX4939
48
32
16
0
14
14