TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 699

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

CRYPT
26.3. CIPHER Operation Mode
26.3.1. CBC Mode
There are two mode in DES and AES engine, they are ECB mode and CBC mode. For CBC mode, it needs to use initial
data for the first calculation, thereafter it uses the previous output result for the initial data. Therefore in CBC mode of DES
and AES, the controller will update the Initial Data field after each calculation.
26.3.2. AES Special Mode
For AES engine, the controller has a special mode that allows the controller to update the KEYs field with the caculated data.
With this feature, the original KEY can be encrypted. Then with the AES decrypt mode, it decrypts the encrypted KEY to get
the original KEY and update the KEY0,1,2,3 fields.
aes_ctrl[7] is the control register bit for this special mode. After this bit is set, the first output data for this index will be saved
back into this index KEY fields
26.4. CIPHER Descriptor
All Cipher descriptors are 32-bit,
Rev. 3.1 November 1, 2005
Field
31:0
Field
31:0
Field
31:2
1:0
Calculate_data[31:0]
Calculate_data[63:32]
Calculate_data[95:64]
Calculate_data[127:96]
Name
SourceGA[31:0]
Name
DestGA[31:0]
Name
nxtptr[31:2]
-
Note: New descriptor must start at double word boundary.
Description
Input Source Address Descriptor
Output Destination Address Descriptor
Next Descriptor Pointer Descriptor
Control Descriptor
Index Descriptor
XOR Input Source Address Descriptor 2
Description
Source G-Bus Address[31:0]
Byte addressable
Description
Destination G-Bus Address[31:0]
Byte addressable
Description
Address of the next descriptor.
Null ('h0000_0000) = End of chain.
Reserved.
Table 26-16 Output Destination Address Descriptor
Table 26-17 Next Descriptor Pointer Descriptor
Table 26-15 Input Source Address Descriptor
aes_key0
aes_key1
aes_key2
aes_key3
Table 26-14 Cipher Descriptor Table
26-9
Toshiba RISC Processor
Offset
‘h00/’h08
‘h04/’h0c
‘h08/’h10
‘h0c/’h14
‘h10/’h18
‘h14/’h1c
TX4939
26
26