TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 22

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
Rev. 3.1 November 1, 2005
Figure 23-4 Data input timing of standard format (Sony format); L_ch=H, R_CH=L.............................................. 23-4
Figure 23-5 Data input timing of Left-Justified format; L_ch=H, R_ch=L ............................................................... 23-4
Figure 23-6 Data input timing of I2S data format (Phillips format); L_ch=L, R_ch=H............................................. 23-5
Figure 23-7 MCLK and SCK with Divider Value..................................................................................................... 23-8
Figure 23-8 Sample-data Transmission Mechanism............................................................................................. 23-9
Figure 23-9 Sample-data Reception Mechanism.................................................................................................. 23-9
Figure 24-1 ACLC Module Configuration.............................................................................................................. 24-2
Figure 24-2 Stereo Audio and Optional Modem Connection Diagram .................................................................. 24-3
Figure 24-3 5.1 Channel Audio Connection Diagram ........................................................................................... 24-4
Figure 24-4 Audio Playback Process Flow ............................................................................................................ 24-5
Figure 24-5 Audio Recording Process Flow ......................................................................................................... 24-6
Figure 24-6 Cold Reset and CODEC Ready Recognition .................................................................................... 24-7
Figure 24-7 Sample-data Transmission Mechanism............................................................................................. 24-9
Figure 24-8 Sample-data Reception Mechanism.................................................................................................. 24-9
Figure 24-9 ACCTLEN Register .......................................................................................................................... 24-17
Figure 24-10 ACCTLDIS Register ....................................................................................................................... 24-21
Figure 24-11 ACREGACC ................................................................................................................................... 24-24
Figure 24-12 ACINTSTS Register ....................................................................................................................... 24-25
Figure 24-13 ACSEMAPH Register ..................................................................................................................... 24-28
Figure 24-14 ACGPIDAT Register ...................................................................................................................... 24-29
Figure 24-15 ACGPODAT Register ..................................................................................................................... 24-30
Figure 24-16 ACSLTEN Register........................................................................................................................ 24-31
Figure 24-17 ACSLTDIS Register....................................................................................................................... 24-33
Figure 24-18 ACFIFOSTS Register .................................................................................................................... 24-35
Figure 24-19 ACDMASTS Register .................................................................................................................... 24-37
Figure 24-20 ACDMASEL Register..................................................................................................................... 24-38
Figure 24-21 ACAUDODAT/ACSURRDAT Register ........................................................................................... 24-39
Figure 24-22 ACCENDAT/ACLFEDAT/ACMODODAT Register ......................................................................... 24-40
Figure 24-23 ACAUDIDAT Register.................................................................................................................... 24-41
Figure 24-24 ACMODIDAT Register ................................................................................................................... 24-42
Figure 24-25 ACREVID Register ........................................................................................................................ 24-43
Figure 25-1 On-chip SRAM Block Diagram ........................................................................................................... 25-1
Figure 25-2 Base Address Specification ................................................................................................................ 25-2
Figure 25-3 On-Chip SRAM Control Register........................................................................................................ 25-3
Figure 27-1 Instruction Register ........................................................................................................................... 27-3
Figure 27-2 Shift Direction of the Instruction Register .......................................................................................... 27-3
Figure 27-3 Boundary Scan Register ................................................................................................................... 27-4
Figure 27-4 Device ID Register ............................................................................................................................ 27-4
Figure 27-5 Shift Direction of the Device ID Register ........................................................................................... 27-4
Figure 28-1 MSTCLK Timing Diagram................................................................................................................... 28-4
Figure 28-2 Power On Reset Timing Diagram ....................................................................................................... 28-4
Figure 28-3 Block Diagram of DDR SDRAM Controller......................................................................................... 28-6
Figure 28-4 DRCKOUT Output Skew .................................................................................................................... 28-7
Figure 28-5 DRDQS Timing Parameter ................................................................................................................. 28-7
Figure 28-6 tDSS/tDSH Timing Parameters .......................................................................................................... 28-7
Figure 28-7 tDQSQV/tDQSQIV Timing Parameters .............................................................................................. 28-8
Figure 28-8 ADDR/CMD to DRCKOUT Timing Parameter (Registered DIMMs) ................................................... 28-8
Figure 28-9 DRDQS Edge Arrival Relative to DRDQ............................................................................................. 28-9
Figure 28-10 External Bus Interface Timing Diagram .......................................................................................... 28-10
Figure 28-11 PCI Interface (3.3 V)....................................................................................................................... 28-12
Figure 28-12 PCI Clock Skew.............................................................................................................................. 28-12
Figure 28-13 Timing Diagram: AC-link Interface .................................................................................................. 28-13
Figure 28-14 Timing Diagram: SPI Interface ....................................................................................................... 28-14
Figure 28-15 Register Transfer to/from device .................................................................................................... 28-16
Figure 28-16 Multiword DMA data Transfer to/from device.................................................................................. 28-17
Figure 28-17 Ultra DMA data Transfer to/from device ......................................................................................... 28-19
Figure 28-18 Ethernet Interface Signal Reception............................................................................................... 28-20
Figure 28-19 Ethernet Interface Signal Transmission.......................................................................................... 28-20
Figure 28-20 Ethernet Interface Management Signal Control ............................................................................. 28-21
Figure 28-21 Video Port Transport data input...................................................................................................... 28-22
Figure 28-22 Video port Transport data output .................................................................................................... 28-22
Figure 29-1 Recommended Footprint for heat disspation...................................................................................... 29-2
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Toshiba RISC Processor
TX4939