TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 602

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SPI
20.4.2. SPI Control Register 0 (SPCR0)
Rev. 3.1 November 1, 2005
Bit(s)
31 : 16
15 : 14
13 : 12
11
10
9
8
7:5
4
3
2
Default:
Default:
Name:
Name:
R/W:
R/W:
Bit:
Bit:
Mnemonic
⎯
TXIFL
RXIFL
SILIE
SOEIE
RBSIE
TBSIE
⎯
IFSPSE
⎯
SBOS
31
15
TXIFL
R/W
0
30
14
29
13
Field Name
Reserved
Transmit Interrupt
Fill Level
Receive Interrupt
Fill Level
SPI IDLE
Interrupt Enable
SPI Overrun
Interrupt Enable
Receive Buffer
Fill Interrupt
Enable
Transmit Buffer
Fill Interrupt
Enable
Reserved
Inter Frame
Space prescaler
enable
Reserved
SPI Bit Order
Select
RXIFL
R/W
0
28
12
Figure 20-5 SPI Control Register 0 (SPCR0)
Table 20-5 SPI Control Register 0 (SPCR0)
SILIE SOEIE RBSIE TBSIE
R/W
27
11
0
Description
⎯
Transmit Interrupt Fill Level (Default: 00)
You can issue interrupts according to the number of free space in the Transmitter
FIFO. This field sets the free space count of the Transmitter FIFO at which
interrupts are issued.
00: Issue an interrupt when there is 1 or more free space in the Transmitter FIFO.
01: Issue an interrupt when there are 2 or more free spaces in the Transmitter FIFO.
10: Issue an interrupt when there are 3 or more free spaces in the Transmitter FIFO.
11: Issue an interrupt when there are 4 free spaces in the Transmitter FIFO.
Receive Interrupt Fill Level (Default: 00)
You can issue interrupts according to the number of data in the Receiver FIFO. This
field sets the number of Receiver FIFO data at which to issue an interrupt.
00: Issue an interrupt when there is 1 or more data in the Receiver FIFO.
01: Issue an interrupt when there are 2 or more data in the Receiver FIFO.
10: Issue an interrupt when there are 3 or more data in the Receiver FIFO.
11: Issue an interrupt when there are 4 data in the Receiver FIFO.
SPI IDLE Interrupt Enable (Default: 0)
Enables SPI Idle interrupts.
0: Disable
1: Enable
SPI IDLE Overrun Enable (Default: 0)
Enables SPI Overrun interrupts.
0: Disable
1: Enable
Receive Buffer Fill Interrupt Enable (Default: 0)
This bit specifies whether to signal an interrupt to the Interrupt Controller based on
the number of data actually in the Receiver FIFO or to only display it as a status.
0: Disable (mask)
1: Enable
Transmit Buffer Fill Interrupt Enable (Default: 0)
This bit specifies whether to signal an interrupt to the Interrupt Controller based on
the number of free data actually in the Transmitter FIFO or to only display it as a
status.
0: Disable (mask)
1: Enable
⎯
Inter Frame Space prescaler Enable (Default: 0)
Enables prescaler of the Interframe Delay Time Counter.
0: Disable (× 1)
1: Enable (× 32)
⎯
SPI Bit Order Select (Default: 0)
This bit specifies the bit order of the transfer data.
R/W
26
10
0
R/W
25
9
0
20-10
RESERVED
R/W
24
8
0
R/O
23
7
0
0
R/O
22
6
0
0
R/O
21
5
0
0
IFSPSE
R/W
20
Toshiba RISC Processor
4
0
R/O
19
3
1
0
0xF804
SBOS SPHA SPOL
R/W
18
2
0
R/W
17
1
0
TX4939
R/W
16
0
0
20
20