TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 12

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
CHAPTER 18. DUAL ETHERNET MAC CONTROLLER.............................................................................................. 18-1
CHAPTER 19. QUAD SIO ............................................................................................................................................. 19-1
CHAPTER 20. SPI INTERFACE.................................................................................................................................... 20-1
Rev. 3.1 November 1, 2005
17.6. B
17.7. ATA B
18.1. F
18.2. B
18.3. D
18.4. R
19.1. F
19.2. B
19.3. D
19.4. R
20.1. F
20.2. B
20.3. O
17.5.5. Issuing Timing of Reset Signal................................................................................................................. 17-34
17.5.6. Command Packet Transmission Timing ................................................................................................... 17-35
17.7.1. PIO Mode................................................................................................................................................. 17-37
17.7.2. Multiword DMA Mode ............................................................................................................................... 17-37
18.3.1. Accessing the Ethernet Controller.............................................................................................................. 18-4
18.3.2. Data structure............................................................................................................................................. 18-7
18.3.3. System control model................................................................................................................................. 18-9
18.3.4. Functional overview ................................................................................................................................. 18-10
18.3.5. DMA function block .................................................................................................................................. 18-13
18.3.6. MAC function blocks ................................................................................................................................ 18-13
18.3.7. Memory configuration............................................................................................................................... 18-15
18.3.8. MAC operation ......................................................................................................................................... 18-20
18.3.9. DMA operation ......................................................................................................................................... 18-31
18.4.1. Overview .................................................................................................................................................. 18-35
18.4.2. PCI Configuration Register group ............................................................................................................ 18-38
18.4.3. DMA Control, Status Register group ........................................................................................................ 18-47
18.4.4. Flow Control Register group .................................................................................................................... 18-59
18.4.5. MAC Control, Status Register group ........................................................................................................ 18-61
19.3.1. Overview .................................................................................................................................................... 19-3
19.3.2. Data Format ............................................................................................................................................... 19-3
19.3.3. Serial Clock Generator............................................................................................................................... 19-5
19.3.4. Data Reception .......................................................................................................................................... 19-7
19.3.5. Data Transmission...................................................................................................................................... 19-7
19.3.6. DMA Transfer ............................................................................................................................................. 19-8
19.3.7. Flow Control............................................................................................................................................... 19-8
19.3.8. Reception Data Status ............................................................................................................................... 19-8
19.3.9. Reception Time Out ................................................................................................................................... 19-9
19.3.10. Software Reset......................................................................................................................................... 19-9
19.3.11. Error Detection/Interrupt Signaling ......................................................................................................... 19-10
19.3.12. Multi-Controller System...........................................................................................................................19-11
19.4.1. Line Control Register 0,1,2,3 ................................................................................................................... 19-13
19.4.2. DMA/Interrupt Control Register 0,1,2,3 .................................................................................................... 19-15
19.4.3. DMA/Interrupt Status Register 0,1,2,3...................................................................................................... 19-17
19.4.4. Status Change Interrupt Status Register 0,1,2,3 ...................................................................................... 19-19
19.4.5. FIFO Control Register 0,1,2,3 .................................................................................................................. 19-20
19.4.6. Flow Control Register 0,1,2,3................................................................................................................... 19-21
19.4.7. Baud Rate Control Register 0,1,2,3 ......................................................................................................... 19-23
19.4.8. Transmit FIFO Register 0,1,2,3 ................................................................................................................ 19-24
19.4.9. Receive FIFO Register 0,1,2,3................................................................................................................. 19-25
20.3.1. Operation modes ....................................................................................................................................... 20-3
20.3.2. Transmitter/Receiver .................................................................................................................................. 20-3
20.3.3. Baud Rate Generator ................................................................................................................................. 20-4
20.3.4. Transfer format........................................................................................................................................... 20-5
20.3.5. Interframe Delay Time Counter .................................................................................................................. 20-6
20.3.6. Buffer configuration .................................................................................................................................... 20-7
20.3.7. SPI system errors....................................................................................................................................... 20-7
20.3.8. Interrupts.................................................................................................................................................... 20-7
EATURES
EATURES
EATURES
ASIC
LOCK DIAGRAM
LOCK
LOCK DIAGRAM
ETAILED EXPLANATION
EGISTERS
ETAILED
EGISTERS
PERATIONAL DESCRIPTION
US
O
D
PERATION
IAGRAM
A
E
........................................................................................................................................................... 18-1
........................................................................................................................................................... 19-1
........................................................................................................................................................... 20-1
CCESS
XPLANATION
....................................................................................................................................................... 18-35
....................................................................................................................................................... 19-12
.................................................................................................................................................. 18-2
.................................................................................................................................................. 19-2
.................................................................................................................................................. 20-2
T
S
IMING
ETUP
........................................................................................................................................ 18-4
........................................................................................................................................ 19-3
(ATA/ATAPI-6 S
................................................................................................................................... 17-36
.................................................................................................................................. 20-3
PEC
. V
ALUES
viii
) ...................................................................................... 17-37
Toshiba RISC Processor
TX4939