TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 60
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
Available stocks
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Price
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NSC
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872
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TOSHIBA
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Part Number:
TX4939XBG-400
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TOSHIBA/东芝
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20 000
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National Conventions Used in This Manual
Rev. 3.1 November 1, 2005
Handling of Reserved Bits and Registers
or use any values read from the reserved registers.
should not use any values read from the reserved fields.
Diagnostic Features
not guaranteed.
References
Reserved registers are not intended for general user access. Software should not write the reserved registers
For all registers with fields marked as reserved, software should write a value of 0 to the reserved field and
Any features labeled as “diagnostic features” are intended for evaluation purposes only, and the operation is
64-Bit TX System RISC TX49/H2, TX49/H3, TX49/H4 Core Architecture
MIPS RISC Architecture, Gerry Kane and Joe Heinrich (ISBN 0-13-590472-2)
See MIPS Run, Dominic Sweetman (ISBN 1-55860-410-3)
MIPS Publications
PCI Local Bus Specification Revision 2.2
PCI Bus Power Management Interface Specification Revision 1.1
Audio CODEC ‘97 (AC ‘97) Revision 2.1
SmartMedia™ Physical Format Specifications Web-Online Version 1.00
SMIL (SmartMedia™ Interface Library) Software Edition Version 1.00
ii
Toshiba RISC Processor
TX4939
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