TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 28

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
Rev. 3.1 November 1, 2005
Table 24-19 ACSLTDIS Register ........................................................................................................................ 24-33
Table 24-20 ACFIFOSTS Register...................................................................................................................... 24-35
Table 24-21 ACDMASTS Register...................................................................................................................... 24-37
Table 24-22 ACDMASEL Register ...................................................................................................................... 24-38
Table 24-23 ACAUDODAT/ACSURRDAT Register............................................................................................. 24-39
Table 24-24 ACCENDAT/ACLFEDAT/ACMODODAT Register ........................................................................... 24-40
Table 24-25 ACAUDIDAT Register ..................................................................................................................... 24-41
Table 24-26 ACMODIDAT Register..................................................................................................................... 24-42
Table 24-27 ACREVID Register........................................................................................................................... 24-43
Table 25-1 Access Cycle Count ............................................................................................................................. 25-2
Table 26-1 Cipher DMA Control Registers ............................................................................................................. 26-4
Table 26-2 Control and Status Register (CSR) ...................................................................................................... 26-4
Table 26-3 Initial Descriptor Pointer Register (IDESPtr) ........................................................................................ 26-6
Table 26-4 Current Cipher Descriptor Pointer Register (CDESPtr)........................................................................ 26-6
Table 26-5 Time Out Register (cip_tout) ................................................................................................................ 26-6
Table 26-6 Bus Error Address Register (BusErr) ................................................................................................... 26-6
Table 26-7 XOR Source Lower Register 0(XORSLR)............................................................................................ 26-6
Table 26-8 XOR Source Upper Register 0(XORSUR) ........................................................................................... 26-6
Table 26-9 Context Index Register (cir) ................................................................................................................. 26-7
Table 26-10 Context Data Register (cdr) ............................................................................................................... 26-7
Table 26-11 DES Context Data Register Format ................................................................................................... 26-7
Table 26-12 AES Context Data Register Format ................................................................................................... 26-8
Table 26-13 MD5/SHA1 Context Data Register Format ........................................................................................ 26-8
Table 26-14 Cipher Descriptor Table ..................................................................................................................... 26-9
Table 26-15 Input Source Address Descriptor ....................................................................................................... 26-9
Table 26-16 Output Destination Address Descriptor .............................................................................................. 26-9
Table 26-17 Next Descriptor Pointer Descriptor..................................................................................................... 26-9
Table 26-18 Control Descriptor ............................................................................................................................ 26-10
Table 26-19 Index Descriptor............................................................................................................................... 26-10
Table 26-20 RNG Control and Status Register (RCSR)....................................................................................... 26-17
Table 26-21 RNG Parameter Register (RPR) ...................................................................................................... 26-17
Table 26-22 RDG Debug Register (RDR) ............................................................................................................ 26-17
Table 26-23 RNG Output Register 1 (ROR1)....................................................................................................... 26-18
Table 26-24 RNG Output Register 2 (ROR2)....................................................................................................... 26-18
Table 26-25 RNG Output Register 3 (ROR3)....................................................................................................... 26-18
Table 27-1 EJTAG Interface Function and Operation Code.................................................................................. 27-1
Table 27-2 Bit Configuration of JTAG Instruction Register.................................................................................... 27-3
Table 27-3 JTAG Interface .................................................................................................................................... 27-5
Table 27-4 Instruction ........................................................................................................................................... 27-6
Table 27-5 Register Map ...................................................................................................................................... 27-7
Table 29-1 Thermal Resistance of Via and Vias .................................................................................................... 29-2
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Toshiba RISC Processor
TX4939