TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 629
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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I2S
Each channel has its own control registers bits to control select format it interfaces to.
As mention before, I2SC controller support 16, 18, 20 or 24 bits data format. Below illustrates how these data map within
32 bits data.
There is a register bit to swap the MSB and LSB order for each channel.
Below illustrates how these data map within 32 bits data with Data Channel Swap Option is enable
In I2SC controller the data transfer is in Little Indian. The following illustrates how data and address appears on G bus.
Rev. 3.1 November 1, 2005
16 bits format:
18 bits format:
20 bits format:
24 bits format:
16 bits format:
18 bits format:
20 bits format:
24 bits format:
Figure 23-6 Data input timing of I2S data format (Phillips format); L_ch=L, R_ch=H
D[31:0]
A[3:2]= 2’b00
Audio Data Word = 16-bit
Audio Data Word = 20-bit
Audio Data Word = 24-bit
WS
SCK
SD
SD
SD
First Data =
Second Data =
Data =
Data =
Data =
First Data =
Second Data =
Data =
Data =
Data =
D[63:32]
A[3:2]=2’b01
1
1
1
MSB
MSB
MSB
2
2
2
Bit[15:0] = [MSB:LSB]
Bit[31:16] = [MSB:LSB]
Bit[17:0] = [MSB:LSB]
Bit[19:0] = [MSB:LSB]
Bit[23:0] = [MSB:LSB]
Bit[15:0] = [LSB:MSB]
Bit[31:16] = [LSB:MSB]
Bit[17:0] = [LSB:MSB]
Bit[19:0] = [LSB:MSB]
Bit[23:0] = [LSB:MSB]
L_ch
15
LSB
19
16
LSB
23
20
23-5
LSB
24
1/f
s
1
1
1
MSB
MSB
MSB
2
2
2
Bit[31:18] are not used.
Bit[31:20] are not used.
Bit[31:24] are not used.
Bit[31:18] are not used.
Bit[31:20] are not used.
Bit[31:24] are not used.
R_ch
15 16
LSB
19
LSB
20
23
LSB
24
Toshiba RISC Processor
1
1
1
2
2
2
TX4939
23
23
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