TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 438

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.55. Configuration Data 2 Register (PCICDATA2)
16.4.56. Configuration Data 3 Register (PCICDATA3)
Rev. 3.1 November 1, 2005
Default
Default
Default
Default
NAME
NAME
NAME
NAME
TYPE
TYPE
TYPE
TYPE
Bits
31:16
15:0
Bits
31:24
23:16
15:8
7:0
Mnemonic
SSID
SSVID
Mnemonic
ML
MG
IP
HT
31
15
31
15
30
14
30
14
Field Name
Sub System ID
Sub System
Vendor ID
Field Name
Maximum Latency Max_Lat (Maximum Latency) (Default: 0x00)
Minimum Grant
Interrupt Pin
Header Type
29
13
29
13
28
12
28
12
0x00
0x00
R/W
R/W
ML
IP
Figure 16-67 PCI Configuration Register 2
Table 16-69 PCI Configuration Register 2
27
11
27
11
Figure 16-66 Sub System ID Register
Table 16-68 Sub System ID Register
Description
Subsystem ID (Default: 0x0000)
This is the data loaded in the Sub System ID Register of the PCI
Configuration space.
Subsystem Vendor ID (Default: 0x0000)
This is the data loaded in the Sub System Vendor ID Register of the PCI
Configuration space.
Description
This is the data loaded in the Max_Lat Register of the PCI Configuration
Space.
Min_Gnt (Minimum Grant) (Default: 0x00)
This is the data loaded in the Min_Gnt Register of the PCI Configuration
Space.
Interrupt Pin (Default: 0x00)
This is the data loaded in the Interrupt Pin Register of the PCI Configuration
Space.
Header Type (Default: 0x00)
This is the data loaded in the Header Type Register of the PCI Configuration
Space.
26
10
26
10
25
25
9
9
16-74
24
24
8
8
0x0000
0x0000
SSVID
SSID
R/W
R/W
23
23
7
7
22
22
6
6
21
21
5
5
20
20
Toshiba RISC Processor
4
4
0x00
0x00
R/W
R/W
MG
HT
19
19
3
3
18
18
2
2
17
17
1
1
TX4939
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
16
16
0
0
16
16