TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 429

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.4.44. PCI Controller Interrupt Mask Register (PCICMASK)
Rev. 3.1 November 1, 2005
Default
Default
NAME
NAME
Bit
31:11
10
9
8
7
6
5
4
3
2:0
TYPE
TYPE
Mnemonic
PMEIE
TLBIE
NIBIE
ZIBIE
PERRIE
SERRIE
GBEIE
31
15
30
14
RESERVED
Field Name
Rsvd
PME Detect
Interrupt Enable
Long Burst
Transfer Detect
Interrupt
Negative
Increment Burst
Transfer Detect
Interrupt Enable
Zero Increment
Burst Transfer
Detect Interrupt
Enable
Rsvd
PERR* Detect
Interrupt Enable
SERR* Detect
Interrupt Enable
G-Bus Bus Error
Detect Interrupt
Enable
Rsvd
29
13
Figure 16-55 PCI Controller Interrupt Mask Register
Table 16-56 PCI Controller Interrupt Mask Register
28
12
27
11
Description
PME* Signal Interrupt Enable (Default: 0x0)
This bit generates an interrupt when input of the PME* signal is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
Too Long Burst Interrupt Enable (Default: 0x0)
This bit generates an interrupt when a Burst transfer by the on-chip DMA
Controller exceeding 8 DWORDs was detected.
1: Generates an interrupt.
0: Does not generate an interrupt
Negative Increment Burst Interrupt Enable (Default: 0x0)
This bit generates an interrupt when a negative direction Burst transfer by the
on-chip DMA Controller is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
Zero Increment Burst Interrupt Enable (Default: 0x0)
This bit generates an interrupt when a Burst transfer by the on-chip DMA
Controller without an address increment is detected.
1: Generates an interrupt.
0: Does not generate an interrupt.
PERR* Interrupt Enable (Default: 0x0)
This bit generates an interrupt when the Parity Error signal (PERR*) is
asserted.
1: Generates an interrupt.
0: Does not generate an interrupt.
SERR* Interrupt Enable (Default: 0x0)
This bit generates an interrupt when the System Error signal (SERR*) is
asserted.
1: Generates an interrupt.
0: Does not generate an interrupt.
G-Bus Bus Error Interrupt Enable (Default: 0x0)
This bit generates an interrupt when a Bus Error is asserted while the PCI
Controller is the G-Bus Master.
1: Generates an interrupt.
0: Does not generate an interrupt.
PMEIE TLBIE NIBIE ZIBIE Rsvd PERRIE SERRIE GBEIE
R/W
0x0
26
10
R/W
0x0
25
9
16-65
RESERVED
R/W
0x0
24
8
R/W
0x0
23
7
22
6
R/W
0x0
21
5
R/W
0x0
20
Toshiba RISC Processor
4
R/W
0x0
19
3
18
2
RESERVED
17
1
R/W
⎯
R/W
R/W
R/W
R/W
⎯
R/W
R/W
R/W
⎯
TX4939
16
0
16
16