TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 534

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.2.6. PCI Control Register (PCI_Ctl) 0x0C
Hardware reset initializes the PCI Control Register to 0x8000_0000. Software reset does not change the register
contents.
BIST is used for testing the buffers on the chip. Bit 31 of the BIST field is read only and is fixed to "1". In other words, the
Ethernet Controller supports BIST. Bit 30 is used to start invoking BIST. Writing "1" to bit 30 starts a test. This bit is
cleared when a test ends. If an error occurs in a test, then either bit 25 or bit 24 is set. Bit 25 is set if a parity error occurs
when starting up SRAM inside DMA. Bit 24 indicates that there is a fault in the SRAM in DMA. In other words, it indicates
that the read data and the expected value (read data) do not match. Bits 29:26 are reserved.
The software driver invokes BIST during initialization. (Note: Invoking BIST affects operation since RAM data and RAM
registers are overwritten.)
When the clock is 33 MHz, testing 1 K × 4-Byte memory requires approximately 123 µs.
The default value of the latency timer is 0. You can use a program to set the latency timer.
After performing a hardware reset, the cache line size is initialized to 0. You must use the software driver to set an
appropriate default value. In most cases, the recommended value is 8 double words (32 Bytes). The maximum value of
the cache line size is 127 double words. The cache line size is used to select the Memory Read Multiple command or
Memory Read Line command and perform Burst reads.
Rev. 3.1 November 1, 2005
Bits
31 : 24
23 : 16
15 : 8
7
6 : 0
Default
Default
Name
Name
TYPE
TYPE
31
15
R
1
Mnemonic
BIST
Hdr_Typ
Lat_Timr
Cache_Sz
BIST
R/W
30
14
0
29
13
Field Name
Embedded Self-Test
Header Type
Latency Timer
Reserved
Cache Line Size
RESERVED
28
12
Lat_Timr
0x00
R/W
27
11
Figure 18-24 PCI Control Register
26
10
25
9
18-42
BIST
0x0
R
Description
BISAT (Default: 0x80, R/W)
Controls whether to invoke BIST during startup.
Hdr_Typ (fixed to "0x00", R)
This is a single-function device. The range 0x10-0x3F of the
configuration space is the standard layout.
Lat_Tmr (DefaultA: 0x00, R/W)
Sets the time the Ethernet Controller operates as the Bus Master
as a PCI Bus Clock count.
Cache_Sz (Default: 0x00, R/W)
Sets the system cache line size.
24
8
Rsvd
23
7
22
6
21
5
20
Hdr_Typ
4
Toshiba RISC Processor
0x00
Cache_Sz
R
0x00
R/W
19
3
18
2
17
1
TX4939
16
0
18
18