TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 576

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

SIO
19.3.11. Error Detection/Interrupt Signaling
An interrupt is signaled if an error or an interrupt cause is detected, the corresponding status bit is set and the corresponding
Interrupt Enable bit is set.
The following figure shows the relationship between the status bit for each interrupt cause and each interrupt enable bit.
Please refer to the explanation for each status bit for more information about each interrupt cause.
Rev. 3.1 November 1, 2005
To IRC
DMAC
DMAC
Transmission DMA Acknowledge
Transmission DMA Acknowledge
Transmission DMA Request
Reception DMA Acknowledge
Figure 19-4 Relationship Between Interrupt Status Bits and Interrupt Signals
SIDISR.STIS
SIDICR.TIE
SIDICR.RIE
SIDICR.SPIE
R
“0” Write
SIDISR.ERI
“0” Write
R
“0” Write
“0” Write
SIDICR.TDE
SIDICR.RDE
19-10
SIDICR.STIE[4]
SISCISR.CTSS
SISCISR.OERS
SIDICR.STIE[5]
SISCISR.RBRKD
SIDICR.STIE[3]
SISCISR.TRDY
SIDICR.STIE[2]
SIDICR.STIE[1]
SISCISR.UBRKD
SIDICR.STIE[0]
SISCISR.TXALS
SIDISR.TOUT
SIDSR.TDIS
SIDISR.RDIS
R
R
R
“0” Write
R
SIDICR.CTSAC
R
S
“0” Write
“0” Write
CTS Pin
Toshiba RISC Processor
Overrun Error
CTS Status
During Break Reception
Transmission Data Empty
Transmission Complete
Break Detected
Frame Error
Parity Error
Reception Time Out
Reception Data Full
Transmission Data Empty
TX4939
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