TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 6

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Index
CHAPTER 6. ADDRESS MAPPING................................................................................................................................ 6-1
CHAPTER 7. CONFIGURATION REGISTERS ............................................................................................................... 7-1
Rev. 3.1 November 1, 2005
5.1. O
5.2. M
5.3. A
5.4. S
5.5. SSCG (S
5.6. D
6.1. TX49 CPU A
6.2. P
6.3. DDR SDRAM M
6.4. PCI A
6.5. R
6.6. R
7.1. D
7.2. R
5.3.1. Features......................................................................................................................................................... 5-3
5.3.2. Source Clock Generation ............................................................................................................................... 5-4
5.3.3. Frequency Error in the Generation of Source Clock out of 20 MHz ............................................................... 5-5
5.3.4. Restriction of Audio Clock for Over Sampling ................................................................................................ 5-7
5.3.5. Audio Clock Control Register ......................................................................................................................... 5-9
5.3.6. MCLKOSC Register ....................................................................................................................................... 5-9
5.3.7. MCLKCTL Register .......................................................................................................................................5-11
5.5.1. SSCG UNIT ................................................................................................................................................. 5-13
5.5.2. Modulation Profile ........................................................................................................................................ 5-13
5.6.1. Theory of Operation ..................................................................................................................................... 5-14
5.6.2. DDR Clock De-Skew.................................................................................................................................... 5-14
5.6.3. PCI Clock De-Skew...................................................................................................................................... 5-15
6.3.1. Fundamentals ................................................................................................................................................ 6-3
6.3.2. Control Registers ........................................................................................................................................... 6-3
6.3.3. DDR Mapping Window Control (DRWINEN)
6.3.4. DDR Mapping Window #n (n=0, 1, 2, 3) DRWIN00
6.4.1. P2G Memory Space (n) PCI Lower Base Address Register (n=0,1,2) ........................................................... 6-7
6.5.1. Addressing ..................................................................................................................................................... 6-9
6.5.2. Endianness and Register size........................................................................................................................ 6-9
6.6.1. Registers for ATA0 ........................................................................................................................................6-11
6.6.2. Registers for ATA1 ....................................................................................................................................... 6-12
6.6.3. Registers for NAND Controller (NDFMC)..................................................................................................... 6-12
6.6.4. Registers for SRAM Controller (SRAMC)..................................................................................................... 6-13
6.6.5. Registers for Crypt Engine Controller........................................................................................................... 6-13
6.6.6. Registers for PCI Controller for ETHERC (PCIC1) ...................................................................................... 6-14
6.6.7. Registers for DDR SDRAM Controller (DDRC) ............................................................................................ 6-16
6.6.8. Registers for External Bus Controller (EBUSC) ........................................................................................... 6-17
6.6.9. Registers for Video Port Controller (VPC).................................................................................................... 6-17
6.6.10. Registers for DMA Controller (DMAC0)...................................................................................................... 6-18
6.6.11. Registers for DMA Controller (DMAC1)...................................................................................................... 6-19
6.6.12. Registers for PCI Controller (PCIC) ........................................................................................................... 6-20
6.6.13. Registers for GBUS to PCI Interface.......................................................................................................... 6-21
6.6.14. Registers for Chip Configuration ................................................................................................................ 6-22
6.6.15. Registers for Timer(s) ................................................................................................................................ 6-23
6.6.16. Registers for Serial I/O............................................................................................................................... 6-24
6.6.17. Registers for Interrupt Controller (IRC) ...................................................................................................... 6-25
6.6.18. Registers for AC Link ................................................................................................................................. 6-26
6.6.19. Registers for Serial Peripheral Interface (SPI) ........................................................................................... 6-26
6.6.20. Registers for I2C Controller........................................................................................................................ 6-27
6.6.21. Registers for I2S Controller........................................................................................................................ 6-27
6.6.22. Registers for RTC Controller ...................................................................................................................... 6-27
6.6.23. Registers for CIR Controller ....................................................................................................................... 6-27
7.1.1. Detecting G-Bus Timeout ............................................................................................................................... 7-1
7.2.1. Chip Configuration Register (CCFG)
7.2.2. Chip Revision ID Register (REVID)
7.2.3. Pin Configuration Register (PCFG)
7.2.4. Timeout Error Access Address Register (TOEA)
UDIO
ECOND
HYSICAL
E
EGISTER
EGISTER
ETAILED
EGISTERS
VERVIEW
ASTER
-S
DRWIN01 0x8210 DRWIN02 0x8218 DRWIN03
KEW
DDRESS
C
LOCK
C
B
PREAD
D
A
C
............................................................................................................................................................... 5-1
LOCK
AUD RATE
M
M
DDRESS
ESCRIPTION
............................................................................................................................................................. 7-2
IRCUIT
AP
AP
DDRESS
G
S
...................................................................................................................................................... 6-10
C
ENERATOR
PACE
G
S
APPING
ONVENTION
ENERATOR
PECTRUM
................................................................................................................................................. 5-14
M
G
M
S
AP
ENERATOR
PACE
............................................................................................................................................ 7-1
APPING
.......................................................................................................................................... 6-3
O
....................................................................................................................................... 5-3
VERVIEW
C
.................................................................................................................................... 5-2
.................................................................................................................................... 6-1
.................................................................................................................................... 6-9
LOCK
................................................................................................................................. 6-7
............................................................................................................................ 5-12
G
.......................................................................................................................... 6-2
ENERATOR
0xE010 ............................................................................................ 7-8
0xE008............................................................................................ 7-7
) .................................................................................................... 5-13
0xE000.......................................................................................... 7-3
ii
0x8200 .............................................................................. 6-4
0xE018.........................................................................7-11
0x8208
0x8220 ...................................................................... 6-5
Toshiba RISC Processor
TX4939