TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 531

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

EMAC
18.4.2.3. PCI Command Register (PCI_Cmd) 0x04
Hardware reset initializes the PCI Command Register to 0x0000. Software reset does not initialize the register contents.
The PCI Command Register defines the method of generating and responding to PCI cycles. For details, see Subsection
6.2.2 Device Control in the PCI 2.2 specification.
For the Ethernet Controller to function properly, you have to set the BusMas bit and MemS bit or IOS bit.
Set the SErrEn bit and the ParER bit to match the system.
The FastEn, WaitCC, VGA_PS, MWIEn and SpecC bits are always "0". The Ethernet Controller ignores any writes to
these bits.
The Ethernet Controller has only one address comparator. The address comparator shares memory access and I/O
access as described below. If MemS=0 and IOS=1, the Ethernet Controller responds to any accesses made to the I/O
space. If MemS=0 and IOS=0, the Ethernet Controller does not respond to any accesses made to the I/O space or to the
memory space. If MemS=1, then the Ethernet Controller only responds to accesses made to the memory space
regardless of the IOS value. Also, you have to initialize the corresponding base address registers in addition to MemS
and IOS.
Rev. 3.1 November 1, 2005
Bit(s)
15 : 10
9
8
7
6
5
4
3
2
1
0
Default
Default
Name
TYPE
Name
TYPE
31
15
Mnemonic
FastEn
SErrEn
WaitCC
ParER
VGA_PS
MWIEn
SpecC
BusMas
MemS
IOS
30
14
RESERVED
29
13
Field Name
Reserved
Fast Back-to-back Enable
System Error Enable
Wait Cycle Control
Parity Error Response
VGA Palette Snoop
Memory Write and Invalidate
Enable
Special Cycle
Bus Master
Memory Space
I/O Space
28
12
Figure 18-21 PCI Command Register
27
11
26
10
FastEn SErrEn WaitCC ParER VGA_PS MWIEn SpecC BusMas MemS
25
R
9
0
18-39
RESERVED
Description
FastEn (fixed to "0", R)
The Ethernet Controller cannot perform two consecutive bus
transactions.
SerrEn (Default: 0, R/W)
Enables the system error (SERR#) driver.
WaitCC (fixed to "0", R)
The Ethernet Controller does not generate address/data
stepping.
ParER (Default: 0, R/W)
The device responds to a parity error.
VGA_PS (fixed to "0", R)
Does not perform special VGA Palette Snoop.
MWIEn (Default: 0, R)
The Ethernet Controller does not issue the Memory Write and
Invalidate command.
SpecC (fixed to "0", R)
The Ethernet Controller ignores special cycles.
BusMas (Default: 0, R/W)
The device can operate as a Bus Master.
MemS (Default: 0, R/W)
The device responds to memory access.
IOS (Default: 0, R/W)
The device responds accesses to the I/O space.
R/W
24
8
0
23
R
7
0
R/W
22
6
0
21
5
R
0
20
R
4
0
Toshiba RISC Processor
19
R
3
0
R/W
18
2
0
R/W
17
1
0
TX4939
R/W
IOS
16
0
0
18
18