TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 204
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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EBC
9.2.9.
External devices connected to the external bus can use the SYSCLK signal as the clock. The SYSCLK signal clock
frequency can be set to one of the following divisions of the internal bus clock (GBUSCLK): 1/3, 1/4, 1/5, 1/6. The SA[4:3]
signal are used to set this frequency during reset, and the setting is reflected in the SYSCLK Division Ratio field
(CCFG.SYSSP) of the Chip Configuration Register.
The operation reference clock frequency can be set to one of the following divisions of the internal bus clock (GBUSCLK)
for each channel independent of the SYSCLK signal clock frequency: 1/3, 1/4, 1/5, 1/6. The external signal of the External
Bus Controller operates synchronous to this operation clock. The Bus Speed field (EBCCRn.SP) of the External Bus
Channel Control Register sets this frequency.
Please set the same value as CCFG.SYSSP to EBCCRn.SP when the external device uses the SYSCLK signal. If these
two values do not match, then the channel, the operation reference clock, and the SYSCLK signal will no longer be
synchronous and will not operate properly.
9.2.10.
TX4939 supports ISA I/O space access. Since the pins used in ISA mode are multiplexed pins, select ISA before use of
these pins.
9.2.10.1.
In the channel set to EBCCRn.ISA=1, 64 Kbyte from the start address of the channel is used for the ISA I/O space. (Refer
to Figure 9-14). When access to the ISA I/O space is performed, IOR* and IOW* control signals are valid, and OE* and
SWE* are invalid. Other control signals are usable, that is the same as the case other than the ISA mode.
Rev. 3.1 November 1, 2005
ISA-16 Space
64 Kbyte
Clock Options
ISA Mode (16-bit only)
Address space
Offset Address
Figure 9-14 Physical Address Mapping of the ISA Spaces
0x010000
0x000000
Normal Channel Space
ISA Space
9-14
Channel End Address
Channel Start Address
Toshiba RISC Processor
Rev 2.13
TX4939
9
9
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