TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 650

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

Toshiba RISC Processor
ACLINK
TX4939
24.3.4. CODEC Register Access
By accessing registers in the CODEC, the system software is able to detect or control the CODEC state.
This section
describes how to read and write CODEC registers via ACLC.
For details about AC’97 register set and proper sequence
to operate CODEC, refer to the AC’97 specification and target CODEC datasheet.
It takes several frame periods for a read or write access to complete.
Taking this into account, ACLC is equipped with a
function for reporting CODEC register access completion as status-change or interrupt.
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In order to read an AC’97 register, write the access destination CODEC ID and register address in ACLC CODEC
Register Access Register (ACREGACC) with its CODECRD bit set to “1”.
After the ACLC Interrupt Status Register
(ACINTSTS)’s REGACC Ready (REGACCRDY) bit is set, the software is able to get the data returned from the AC’97 by
reading the ACREGACC register and issue another access.
In order to write to an AC’97 register, write the access destination CODEC ID, register address, and the data in ACLC’s
ACREGACC register with ACREGACC.CODECRD bit set to “0”.
After the ACINTSTS.REGACCRDY bit has been set,
the software is able to issue another access.
In case of 5.1 channel audio connection example (Figure 24-3), because the secondary CODEC has CODEC ID of ‘3’,
the software must write ‘3’ into ACREGACC.CODECID field when it issues secondary CODEC register access.
Rev. 3.1 November 1, 2005
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