TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 453

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

PCIC
16.6. A Malfunction of PCI Controller
16.6.1. Outline of the problem
If PCI to G-Bus transfer (PCI initiator read) by PDMAC, PCI read access by G-Bus bus master (B), and PCI bus access (read
or write) by G-Bus bus master (A) are executed simultaneously, PCI read access by G-Bus bus master (B) could not finish.
16.6.2. Condition of the problem occurrence
16.6.3. Work-around
In case of that PCI to G-Bus transfer (PCI initiator read) by PDMAC and PCI read access by G-Bus bus master (B) are
executed simultaneously, any PCI bus access (read or write) is forbidden.
(Any problem doesn’t occur if the number of G-Bus bus master which executes PCI read access simultaneously with
PDMAC is one, or if the G-Bus bus masters execute PCI write access regardless of the number of the G-Bus bus masters).
Rev. 3.1 November 1, 2005
(1)
(2)
(3)
(4)
PDMAC PCI Initiator reads data from a device on PCI bus. (Read from PCI bus and write to G-Bus.)
If an access (read or write) requirement (*) to a device on PCI bus by G-Bus bus master (A) is issued
before PDMAC PCI initiator’s read transfer (1) finish, the required access by G-Bus bus master (A) will
be retried on G-Bus.
By the way, the retry happened by overflow of PCI access command queue could cause the problem.
The followings are candidates to cause that retry.
The access requirement (*) by G-Bus bus master (A) is :
PDMAC initiator read transfer (1) finish on PCI bus.
Though read transfer on PCI bus by G-Bus bus master (B) is executed, it will be retried, and then the
retry can’t be accepted. Then retry → refuse the request → retry → refuse the request → … This
iteration will be continued permanently.
□ Burst Write Transfer
□ Single write transfer in case of that three times single write transfers are executed before
□ (Single/Burst) read transfer in case of that three times single write transfers are executed
PDMAC PCI initiator read transfer (1)
before PDMAC PCI initiator read transfer (1)
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Toshiba RISC Processor
TX4939
16
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