MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 100

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

i.MX28 Product Features
1.3.6 Interrupt Collector
The i.MX28 contains a 128-bit vectored interrupt collector for the CPU's IRQ input and a
separate non-vectored interrupt collection mechanism for the CPU's FIQ input. Each interrupt
can be assigned to one of the four levels of priority. The interrupt collector supports nesting
of interrupts that preempt an interrupt service routine running at a lower priority level. Each
of the 128 interrupts is assigned its own 32-bit programming register and can be set for HW
source IRQ, SW source IRQ or HW source FIQ.
See
1.3.7 Default First-Level Page Table
The device contains a default first-level page table (DFLPT) implemented as an AHB slave.
This device provides an economical way to present 16 Kbytes of L1 page table entry data
to the ARM CPU's MMU. This page-table is connected to the AHB bus at base address
0x800C0000. The DFLPT provides 16 movable and scalable entries such that each entry
can span up to128 locations. This allows the DFLPT to be used for systems with large
external memories.
See
1.3.8 DMA Controller
Many peripherals on the i.MX28 use direct memory access (DMA) transfers. Some
peripherals, such as the USB controller, make high random accesses to the system memory
for a large number of descriptor, queue heads, and packet payload transfers. This high
random access nature is supported by integrating a dedicated DMA into the USB controller
and connecting it directly to the high-speed AHB bus.
Similarly, the DCP (crypto/memcpy), BCH-ECC and LCD controller (legacy DMA mode)
devices contain their own bus masters to allow more random accesses to the system memory.
Other peripherals have small number of high sequential transactions, for example the ADC
streams, SPDIF transmitter, and so on. These devices share a centralized address generation
and a data transfer function that allows them to share a single shared master on the AHB.
As mentioned previously, there are two AMBA peripheral buses on the i.MX28:
100
• The APBH bus runs at 200 MHz clock domain.
• The APBX bus runs in an independent XCLK clock domain that can be slowed down
Interrupt Collector (ICOLL) Overview
Default First-Level Page Table (DFLPT) Overview
significantly for power reduction.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
for additional information.
for additional information.
Freescale Semiconductor, Inc.