MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1577

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Starting with the last event, FlexCAN attempts to synchronize to the CAN bus.
25.6 Programmable Registers
CAN Hardware Register Format Summary
There are Two CAN in chip. CAN0 base address is 0x80032000 and CAN1 base address
is 0x80034000
Freescale Semiconductor, Inc.
8003_201C
8003_2000
8003_2004
8003_2008
8003_2010
8003_2014
8003_2018
8003_2020
8003_2024
8003_2028
Absolute
• Initialize the Message Buffers
• Initialize the Rx Individual Mask Registers
• Set required interrupt mask bits in the IMASK Registers (for all MB interrupts), in
• Negate the HALT bit in MCR
address
(hex)
CTRL Register (for Bus Off and Error interrupts) and in MCR Register for Wake-Up
interrupt
• Determine the bit rate by programming the PRESDIV field
• Determine the internal arbitration mode (LBUF bit)
• The Control and Status word of all Message Buffers must be initialized
• If FIFO was enabled, the 8-entry ID table must be initialized
• Other entries in each Message Buffer should be initialized as required
Module Configuration Register (HW_CAN_MCR)
Control Register (HW_CAN_CTRL)
Free Running Timer (HW_CAN_TIMER)
Rx Global Mask (HW_CAN_RXGMASK)
Rx 14 Mask (HW_CAN_RX14MASK)
Rx 15 Mask (HW_CAN_RX15MASK)
Error Counter Register (HW_CAN_ECR)
Error and Status Register (HW_CAN_ESR)
Interrupt Masks 2 Register (HW_CAN_IMASK2)
Interrupt Masks 1 Register (HW_CAN_IMASK1)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_CAN memory map
Chapter 25 Controller Area Network (FlexCAN)
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFFF_FFFFh
FFFF_FFFFh
FFFF_FFFFh
Reset value
5890_000Fh
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
25.6.10/1588
25.6.1/1578
25.6.2/1580
25.6.3/1582
25.6.4/1583
25.6.5/1583
25.6.6/1584
25.6.7/1584
25.6.8/1586
25.6.9/1587
Section/
page
1577