MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1891
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
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29.9.51 ENET SWI Port 1 VLAN priority resolution map
Port 1 VLAN priority resolution map. The 3-bit to 3-bit priority map addressed by the
priority bits of the VLAN tag
The VLAN_PRIORITY1 registers implement a 3-bit to 3-bit VLAN priority mapping
capability. The current frame's 3-bit VLAN priority field is used as an index and the
corresponding priority is taken from the respective position of the register giving the final
classification for the frame.
Address:
Re-
Freescale Semiconductor, Inc.
set
Bit
W
R
31
RSRVD0
0
23 21
20 18
17 15
14 12
31 24
Field
11 9
Field
8 6
5 3
2 0
P7
P6
P5
P4
P3
P2
P1
P0
30
0
29
0
RSRVD0
HW_ENET_SWI_VLAN_PRIORITY1
8104h
(HW_ENET_SWI_VLAN_PRIORITY1)
28
0
HW_ENET_SWI_VLAN_PRIORITY0 field descriptions (continued)
Priority for input priority 7
Priority for input priority 6
Priority for input priority 5
Priority for input priority 4
Priority for input priority 3
Priority for input priority 2
Priority for input priority 1
Priority for input priority 0
Reserved bits. Write as 0.
27
0
26
0
HW_ENET_SWI_VLAN_PRIORITY1 field descriptions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
0
24
0
23
0
P7
22
0
21
0
20
0
P6
19
0
Chapter 29 Programmable 3-Port Ethernet Switch with QOS (SWITCH)
18
800F_8000h base + 104h offset = 800F_
0
17
0
P5
16
0
15
0
Description
Description
14
0
P4
13
0
12
0
11
0
P3
10
0
0
9
0
8
P2
0
7
0
6
0
5
P1
0
4
3
0
0
2
P0
0
1
1891
0
0
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