MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 889

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

10.8.26 Clock Frequency Sequence Control Register
The CLKSEQ control register provides control for switching between XTAL and PLL clock
generation.
HW_CLKCTRL_CLKSEQ: 0x1D0
HW_CLKCTRL_CLKSEQ_SET: 0x1D4
HW_CLKCTRL_CLKSEQ_CLR: 0x1D8
HW_CLKCTRL_CLKSEQ_TOG: 0x1DC
This register controls the selection of clock sources (ref_xtal or ref_*) for various clock
dividers.
EXAMPLE
HW_CLKCTRL_CLKSEQ_WR(BF_CLKCTRL_CLKSEQ_BYPASS_SAIF0(1));
Address:
Freescale Semiconductor, Inc.
Reset
PIX_STABLE
Bit
W
R
PIXFRAC
Field
5 0
6
31
0
HW_CLKCTRL_CLKSEQ 8004_0000h base + 1D0h offset = 8004_01D0h
(HW_CLKCTRL_CLKSEQ)
30
0
This read-only bitfield is for DIAGNOSTIC PURPOSES ONLY since the fractional divider should become
stable quickly enough that this field will never need to be used by either device driver or application code.
The value inverts when the new programmed fractional divide value has taken effect. Read this bit, program
the new value, and when this bit inverts, the phase divider clock output is stable. Note that the value will
not invert when the fractional divider is taken out of or placed into clock-gated state.
This field controls the PIX clock fractional divider. The resulting frequency shall be 480 * (18/PIXFRAC)
where PIXFRAC = 18-35.
29
HW_CLKCTRL_FRAC1 field descriptions (continued)
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
0
27
0
26
0
RSRVD0
25
0
24
0
Description
Chapter 10 Clock Generation and Control (CLKCTRL)
23
0
22
1
21
0
20
0
19
0
18
1
17
RSRVD1
0
[17:16]
16
0
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