MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1402
![no-image](/images/manufacturer_photos/0/2/262/freescale_semiconductor_sml.jpg)
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
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- MCIMX283DVM4B PDF datasheet #3
- MCIMX283DVM4B PDF datasheet #4
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- Download datasheet (17Mb)
Programmable Registers
Address:
Re-
19.4.44 AHB Layer 2 Transfer Count Register
The AHB Layer 2 Transfer Count Register counts the number of AHB bus cycles during
which a transfer is active on AHB Layer 2.
This field counts the number of AHB cycles in which a master was requesting a transfer,
and the slave had not responded. This includes cycles in which it was requesting transfers
but was not granted them, as well as cycles in which it was granted and driving the bus but
the targeted slave was not ready. The master selects in
HW_DIGCTL_CTRL_MASTER_SELECT are used in the arbiter to mask which master\'s
cycles are actually recorded here.
EXAMPLE
NumberCycles = HW_DIGCTL_L2_AHB_ACTIVE_CYCLES_COUNT_RD();
Address:
Re-
1402
set
set
Bit
Bit
W
W
R
R
31
31
0
0
COUNT
Field
31 0
30
30
0
0
ElapsedTime = HW_DIGCTL_HCLKCOUNT_RD() - StartTime;
29
29
0
0
HW_DIGCTL_L1_AHB_DATA_CYCLES
8001_C390h
HW_DIGCTL_L2_AHB_ACTIVE_CYCLES
8001_C3A0h
(HW_DIGCTL_L2_AHB_ACTIVE_CYCLES)
28
28
0
0
This field contains the count of AHB bus cycles during which data was actually transferred from a master
to a slave or from a slave to a master.
27
27
0
0
HW_DIGCTL_L1_AHB_DATA_CYCLES field descriptions
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
24
24
0
0
23
23
0
0
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
0
0
8001_C000h base + 390h offset =
17
17
0
0
8001_C000h base + 3A0h offset =
COUNT
COUNT
16
16
0
0
15
15
0
0
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0
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