MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2271

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

38.5 Programmable Registers
LRADC Hardware Register Format Summary
38.5.1 LRADC Control Register 0 (HW_LRADC_CTRL0)
The LRADC Control Register 0 provides overall control of the eight low resolution analog
to digital converters.
Freescale Semiconductor, Inc.
8005_00C0
8005_00D0
8005_0000
8005_0010
8005_0020
8005_0030
8005_0040
8005_0050
8005_0060
8005_0070
8005_0080
8005_0090
8005_00A0
8005_00B0
8005_00E0
8005_00F0
8005_0100
8005_0110
8005_0120
8005_0130
8005_0140
8005_0150
8005_0160
8005_0170
Absolute
address
(hex)
LRADC Control Register 0 (HW_LRADC_CTRL0)
LRADC Control Register 1 (HW_LRADC_CTRL1)
LRADC Control Register 2 (HW_LRADC_CTRL2)
LRADC Control Register 3 (HW_LRADC_CTRL3)
LRADC Status Register (HW_LRADC_STATUS)
LRADC 0 Result Register (HW_LRADC_CH0)
LRADC 1 Result Register (HW_LRADC_CH1)
LRADC 2 Result Register (HW_LRADC_CH2)
LRADC 3 Result Register (HW_LRADC_CH3)
LRADC 4 Result Register (HW_LRADC_CH4)
LRADC 5 Result Register (HW_LRADC_CH5)
LRADC 6 Result Register (HW_LRADC_CH6)
LRADC 7 (BATT) Result Register (HW_LRADC_CH7)
LRADC Scheduling Delay 0 (HW_LRADC_DELAY0)
LRADC Scheduling Delay 1 (HW_LRADC_DELAY1)
LRADC Scheduling Delay 2 (HW_LRADC_DELAY2)
LRADC Scheduling Delay 3 (HW_LRADC_DELAY3)
LRADC Debug Register 0 (HW_LRADC_DEBUG0)
LRADC Debug Register 1 (HW_LRADC_DEBUG1)
LRADC Battery Conversion Register
(HW_LRADC_CONVERSION)
LRADC Control Register 4 (HW_LRADC_CTRL4)
LRADC Theshold0 Register (HW_LRADC_THRESHOLD0)
LRADC Theshold1 Register (HW_LRADC_THRESHOLD1)
LRADC Version Register (HW_LRADC_VERSION)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_LRADC memory map
Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface
(in bits)
Width
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
C000_0000h
1FFF_0000h
Reset value
0000_0000h
0000_8000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
0000_0000h
4321_0000h
0000_0000h
0000_0080h
7654_3210h
0000_0000h
0000_0000h
0103_0000h
38.5.10/2291
38.5.11/2293
38.5.12/2294
38.5.13/2296
38.5.14/2298
38.5.15/2299
38.5.16/2301
38.5.17/2302
38.5.18/2304
38.5.19/2304
38.5.20/2306
38.5.21/2307
38.5.22/2311
38.5.23/2313
38.5.24/2314
38.5.1/2271
38.5.2/2274
38.5.3/2277
38.5.4/2280
38.5.5/2282
38.5.6/2284
38.5.7/2286
38.5.8/2288
38.5.9/2289
Section/
page
2271