MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1138

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
1138
Reset
INTRPTAPBURST
INTRPTWRITEA
INTRPTREADA
WRITEINTERP
Bit
W
R
RSVD4
RSVD3
RSVD2
RSVD1
31 25
23 17
15 9
Field
7 1
24
16
8
0
15
0
14
0
Always write zeroes to this field.
Allow controller to interrupt a write burst to the DRAMs with a read cmd.
Defines whether the EMI can interrupt a write burst with a read command. Some memory devices do not
allow this functionality.
For DDR1 or LPDDR1 memory devices, consult the memory specification for the setting for this parameter.
For DDR2memory devices, this parameter must be cleared to 'b0.
'b0 = The device does not support read commands interrupting write commands.
'b1 = The device does support read commands interrupting write commands.
Always write zeroes to this field.
Allow the controller to interrupt a combined write with auto pre-charge cmd with another write cmd.
Enables interrupting of a combined write with auto pre-charge command with another read or write command
to the same bank before the first write command is completed.
'b0 = Disable interrupting a combined write with auto pre-charge command with another read or write
command to the same bank.
'b1 = Enable interrupting a combined write with auto pre-charge command with another read or write
command to the same bank.
Always write zeroes to this field.
Allow the controller to interrupt a combined read with auto pre-charge cmd with another read cmd.
Enables interrupting of a combined read with auto pre-charge command with another read command to
the same bank before the first read command is completed.
'b0 = Disable interrupting the combined read with auto pre-charge command with another read command
to the same bank.
'b1 = Enable interrupting the combined read with auto pre-charge command with another read command
to the same bank.
Always write zeroes to this field.
Allow the controller to interrupt an auto pre-charge cmd with another cmd.
Enables interrupting an auto pre-charge command with another command for a different bank. If enabled,
the current operation will be interrupted. However, the bank will be pre-charged as if the current operation
were allowed to continue.
'b0 = Disable interrupting an auto pre-charge operation on a different bank.
13
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
RSVD2
12
0
HW_DRAM_CTL34 field descriptions
11
0
10
0
0
9
0
8
Description
0
7
0
6
5
0
RSVD1
4
0
Freescale Semiconductor, Inc.
0
3
0
2
0
1
0
0