MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1358

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
and unfulfilled bus operation in flight. The Active Cycles register counts the number of
data transfer cycles. Subtract cycles from stalls to determine under utilized bus cycles. These
counters can be used to tune the performance of the HCLK frequency for specific activities.
In addition, these monitors can be forced to focus on specific masters (which connect to
that layer). See the HW_DIGCTL_AHB_STATS_SELECT bit description for details.
19.3.2 High-Entropy PRN Seed
A 32-bit entropy register begins running a pseudo-random number algorithm from the time
reset is removed until the PSWITCH is released by the user. This high-entropy value can
be used as the seed for other pseudo-random number generators.
19.3.3 Write-Once Register
A 32-bit write-once register holds a runtime-derived locked seed. Once written, it cannot
be changed until the next chip wide reset event. The contents of this register are frequently
derived from the entropy register.
19.3.4 Microseconds Counter
A 32-bit free-running microseconds counter provides fine-grain real-time control. Its period
is determined by dividing the 24.0-MHz crystal oscillator by 24. Therefore, its frequency
does not change as HCLK, XCLK, and the processor clock frequency are changed.
19.4 Programmable Registers
DIGCTL Register Format Summary
1358
8001_C000
8001_C010
8001_C020
8001_C030
8001_C040
8001_C050
Absolute
address
(hex)
DIGCTL Control Register (HW_DIGCTL_CTRL)
DIGCTL Status Register (HW_DIGCTL_STATUS)
Free-Running HCLK Counter Register
(HW_DIGCTL_HCLKCOUNT)
On-Chip RAM Control Register (HW_DIGCTL_RAMCTRL)
EMI Status Register (HW_DIGCTL_EMI_STATUS)
On-Chip Memories Read Margin Register
(HW_DIGCTL_READ_MARGIN)
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Register name
HW_DIGCTL memory map
(in bits)
Width
32
32
32
32
32
32
Access
R/W
R/W
R/W
R
R
R
Freescale Semiconductor, Inc.
FF00_0000h
Reset value
0001_0004h
0000_0000h
0000_0000h
0000_0000h
0000_0002h
19.4.1/1361
19.4.2/1364
19.4.3/1366
19.4.4/1367
19.4.5/1368
19.4.6/1369
Section/
page