MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 963

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

// Multi Write Data Command
//
// Creates Write Data Command header which performs writes to multiple taget
// addresses
//
// inputs: flags - DCD command flags
//
//
#define MULTI_WRT_DAT(flags, bytes, number)
// DCD Table definition
uint8_t input_dcd[] = {
//void POWER_Init(void) just pick one register since no impact on RTL
//
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800440b4, 0x00003000),
// PLL already turn on by ROM
// HW_CLKCTRL_FRAC0_CLR(BM_CLKCTRL_FRAC0_CLKGATEEMI);
// Turn on fractional clock control 0 EMI clkgate,
// setmem /32 0x800401b8=0x00008000
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800401b8, 0x00008000),
// Set up the EMI clock
//
//
//
//
// Write the PLL fractional divider W_CLKCTRL_FRAC0_WR(frac_val);
// Clear the EMI frac first
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800401b8, 0x00003F00),
// write new_pll_frac_div
WRT_DAT(0, HAB_DATA_WIDTH_WORD, 0x800401b4, 29 << 8),
// init_dram_regs(); // Write the Databahn SDRAM setup register values
// use mobile_ddr_mt46h32m16lf_5_150MHz_for_dcd.c -- for 150MHz mDDR, 63 entries
MULTI_WRT_DAT(0, HAB_DATA_WIDTH_WORD, 63),
//
EXPAND_UINT32(0x800e0000 + 0 * 4), EXPAND_UINT32(0x00000000),
//
//000_00001 tccd(RW) 0000_0011 trp_ab(RW)
//0000_0001 cksrx(RW) 0000_0001 cksre(RW)
EXPAND_UINT32(0x800e0000 + 177 * 4), EXPAND_UINT32(0x01030101),
//
//0_0100001 axi5_bdw(RW) 0_0000000 axi4_current_bdw(RD)
//0_0100001 axi4_bdw(RW) 000_00001 tckesr(RW)
EXPAND_UINT32(0x800e0000 + 178 * 4), EXPAND_UINT32(0x01001901),
//
//0_000000000110010 mr0_data_1(RW) 0_000000000110010 mr0_data_0(RW)
Freescale Semiconductor, Inc.
HDR(HAB_CMD_WRT_DAT, (number * 2 + 1) * 4, WRT_DAT_PAR((flags), (bytes)))
/* DCD header */
DCD_HDR(HDR_BYTES + 26 * WRT_DAT_BYTES + (63 * 2 + 1) * 4, HAB_VER(4,0)),
HW_POWER_LOOPCTRL.B.EN_RCSCALE = 3;
DRAM_REG[0] =
DRAM_REG[177] =
DRAM_REG[178] =
DRAM_REG[181] =
case EMI_CLK_150MHz:
bytes - size of write by command (1, 2, or 4)
number - number of writes performed by the DCD write data command
use_xtal_src = 0;
new_pll_frac_div = 29;
new_pll_int_div = 2;
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
0x00000000;
0x01030101;
0x01001901;
0x00320032;
.
.
.
.
.
.
\
Chapter 12 Boot Modes
963