MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1003

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

13.2.2 Advanced Encryption Standard (AES)
The AES block implements a 128-bit key/data encryption/decryption block as defined by
the National Institute of Standards and Technology (NIST) as US FIPS PUB 197, dated
November 2001 (see references for specifications and toolkits)
There are three variations of AES, each corresponding to the key size used: AES-128,
AES-192 or AES-256. AES always operates on 128 bits of data at a time. Only the AES-128
algorithm is implemented at this time.
13.2.2.1 Key Storage
The DCP implements four SRAM-based keys that may be used by software to securely
store keys on a semi-permanent basis. The keys may be written through the PIO interface
by specifying a key index to specify which key to load and a subword pointer that indicates
which word to write within the key. After a subword is written, the logic automatically
increments the subword pointer so that software can program the higher-order words of the
key without rewriting the key index. Keys written into the key storage are not readable.
To use a key in the key storage, the cipher descriptor packet should select the key by setting
the KEY_SELECT field in the Control1 descriptor field without setting the OTP_KEY or
PAYLOAD_KEY fields in the Control0 register.
13.2.2.2 OTP Key
After a system reset, the OTP controller reads the e-fuse devices and provides the OTP key
information over a parallel 128-bit interface. The key transfer interface runs on HCLK and
provides the key over the serialized otp_data signal. The otp_crypto_key_smpl signal
indicates when the key value is valid and causes the control logic to capture the key into
the key RAM.
To use the OTP key, the descriptor packet should set the OTP_KEY field in the Control1
register.
1.
Freescale Semiconductor, Inc.
The AES core used in the design was derived from the AES design available from OpenCores.org under a modified BSD
license as described here: http://www.opencores.org/projects.cgi/web/aes_core/overview The license for this code is documented
in
Disclaimer
for compliance.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Chapter 13 Data Co-Processor (DCP)
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