MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1928
MCIMX286CVM4B
Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r
Datasheets
1.MCIMX283DVM4B.pdf
(70 pages)
2.MCIMX283DVM4B.pdf
(2 pages)
3.MCIMX283DVM4B.pdf
(2327 pages)
4.MCIMX283DVM4B.pdf
(20 pages)
Specifications of MCIMX286CVM4B
Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
- MCIMX283DVM4B PDF datasheet
- MCIMX283DVM4B PDF datasheet #2
- MCIMX283DVM4B PDF datasheet #3
- MCIMX283DVM4B PDF datasheet #4
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- Download datasheet (17Mb)
Programmable Registers
Address:
Re-
29.9.106 ENET SWI Port 2 incoming frames discarded due to missing
Port 2 incoming frames discarded due to missing vlan tag. See also Register
VLAN_VERIFY.
Address:
Re-
29.9.107 ENET SWI Port 2 incoming frames discarded (after learning)
(HW_ENET_SWI_IDISC_BLOCKED2)
Port 2 incoming frames discarded (after learning) as port is configured in blocking mode
1928
set
set
Bit
Bit
W
W
R
R
IDISC_VLAN2
UNTAGGED2
31
31
0
0
IDISC_
Field
31 0
Field
31 0
30
30
0
0
29
29
0
0
HW_ENET_SWI_IDISC_VLAN2 800F_8000h base + 334h offset = 800F_8334h
HW_ENET_SWI_IDISC_UNTAGGED2 800F_8000h base + 338h offset = 800F_
8338h
28
28
0
0
vlan tag (HW_ENET_SWI_IDISC_UNTAGGED2)
as port is configured in blocking mod
ENET SWI Port 2 incoming frames discarded due to mismatching or missing VLAN id
ENET SWI Port 2 incoming frames discarded due to missing vlan tag
27
27
0
0
26
26
0
0
HW_ENET_SWI_IDISC_UNTAGGED2 field descriptions
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
HW_ENET_SWI_IDISC_VLAN2 field descriptions
24
24
0
0
23
23
0
0
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
18
18
IDISC_UNTAGGED2
0
0
IDISC_VLAN2
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
Freescale Semiconductor, Inc.
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
0
0
0
0
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