MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1995

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

31.7.27 Host Transmit Pre-Buffer Packet Timing Register
The fields in this register control performance tuning associated with how the host controller
posts data to the TX latency FIFO before moving the data onto the USB bus. The specific
areas of performance include the how much data to post into the FIFO and an estimate for
how long that operation should take in the target system. Definitions: T0 = Standard packet
overhead T1 = Time to send data payload Tff = Time to fetch packet into TX FIFO up to
specified level. Ts = Total Packet Flight Time (send-only) packet Ts = T0 + T1 Tp = Total
Packet Time (fetch and send) packet Tp = Tff + T0 + T1 Upon discovery of a transmit
(OUT/SETUP) packet in the data structures, host controller checks to ensure Tp remains
before the end of the (micro)frame. If so it proceeds to pre-fill the TX FIFO. If at anytime
during the pre-fill operation the time remaining the (micro)frame is < Ts then the packet
attempt ceases and the packet is tried at a later time. Although this is not an error condition
and the host controller will eventually recover, a mark will be made the scheduler health
counter to note the occurrence of a "back-off" event. When a back-off event is detected, the
partial packet fetched may need to be discarded from the latency buffer to make room for
periodic traffic that will begin after the next SOF. Too many back-off events can waste
bandwidth and power on the system bus and thus should be minimized (not necessarily
eliminated). Back-offs can be minimized with use of the TSCHHEALTH (Tff) described
below. This is a read/write register. Writes must be DWORD writes. The default value of
this register is 0x00000000.
Freescale Semiconductor, Inc.
RXPBURST
TXPBURST
31 16
RSVD
Field
15 8
7 0
(HW_USBCTRL_TXFILLTUNING)
Reserved.
These bits are reserved and their value has no effect on operation.
Programmable TX Burst Length.
This register represents the maximum length of a the burst in 32-bit words while moving data from system
memory to the USB bus.
Programmable RX Burst Length.
This register represents the maximum length of a the burst in 32-bit words while moving data from the USB
bus to system memory.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
HW_USBCTRL_BURSTSIZE field descriptions
Chapter 31 USB High-Speed On-the-Go Host Device Controller
Description
1995