MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1296

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Programmable Registers
16.6.8 Hardware BCH ECC Flash 0 Layout 0 Register
The flash format register contains a description of the logical layout of data on the flash
device. This register is used in conjuction with the FLASH0LAYOUT1 register to control
the format for the devices selecting layout 0 in the LAYOUTSELECT register.
Each pair of layout registers describes one of four supported flash configurations. Software
should program the LAYOUTSELECT register for each supported GPMI chip select to
select from one of the fourlayout values. Each pair of registers contains settings that are
used by the BCH block while reading/writing the flash page to control data, metadata, and
flash page sizes as well as the ECC correction level. The first block written to flash can be
programmed to have different ECC, metadata, and data sizes from subsequent data blocks
on the device. In addition, the number of blocks stored on a page of flash is not fixed, but
instead is determined by the number of bytes consumed by the initial (block 0) and
subsequent data blocks. See the BCH programming reference manual for more information
on setting up the flash layout registers.
EXAMPLE
HW_BCH_FLASH0LAYOUT0_WR(0x020C8000);
HW_BCH_FLASH0LAYOUT1_WR(0x04408200);
Address:
Re-
1296
set
Bit
W
R
META_SIZE
NBLOCKS
31
0
31 24
23 16
15 12
ECC0
Field
30
0
29
0
NBLOCKS
(HW_BCH_FLASH0LAYOUT0)
HW_BCH_FLASH0LAYOUT0
28
0
Number of subsequent blocks on the flash page (excluding the data0 block). A value of 0 indicates that only
the DATA0 block is present and a value of 8 indicates that 8 subsequent blocks are present for a total of 9
blocks on the flash (including the DATA0 block). Any values from 0 to 255 are supported by the hardware.
Indicates the size of the metadata (in bytes) to be stored on a flash page. The BCH design support from 0
to 255 bytes for metadata -- if set to zero, no metadata will be stored. Metadata is stored before the associated
data in block 0. If the DATA0_SIZE field is programmed to a zero, then metadata effectively be stored with
its own parity. When both the metadata and data0 fields are programmed with non-zero values, the first
block will contain both portions of data and will be covered by a single parity block.
Indicates the ECC level for the first block on the flash page. The first block covers metadata plus the
associated data from the DATA0_SIZE field.
0x0
27
0
26
1
NONE — No ECC to be performed
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
1
HW_BCH_FLASH0LAYOUT0 field descriptions
24
1
23
0
22
0
21
0
META_SIZE
20
8000_A000h base + 80h offset = 8000_A080h
0
19
1
18
0
17
1
16
0
15
1
Description
ECC0
14
0
13
0
12
0
11
0
10
0
1
9
0
8
Freescale Semiconductor, Inc.
DATA0_SIZE
0
7
0
6
0
5
0
4
3
0
0
2
0
1
0
0