MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1345

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

17.10.16 SD/MMC DLL Control Register (HW_SSP_DLL_CTRL)
SD/MMC Delay Loop Lock Control Register.
This register provides programmability in DDR mode for data input timing and data formats.
Address:
Freescale Semiconductor, Inc.
Reset
Reset
OVERRIDE_VAL
SLV_OVERRIDE
REF_UPDATE_
GATE_UPDATE
SLV_UPDATE_
Bit
Bit
W
W
R
R
RSVD1
RSVD0
31 28
27 20
19 16
15 10
SLV_
Field
INT
INT
9
8
7
31
15
0
0
REF_UPDATE_INT
HW_SSP_DLL_CTRL
30
14
0
0
SLV_OVERRIDE_VAL
This field allows the user to add additional delay cycles to the DLL control loop (reference delay line control).
By default, the DLL control loop shall update every two SSPCLK cycles. Programming this field results in a
DLL control loop update interval of (2 + REF_UPDATE_INT) * SSPCLK. It should be noted that increasing
the reference delay-line update interval reduces the ability of the DLL to adjust to fast changes in conditions
that may effect the delay (such as voltage and temperature)
Setting a value greater than 0 in this field, shall over-ride the default slave delay-line update interval of 256
SSPCLK cycles. A value of 0 results in an update interval of 256 SSPCLK cycles (default setting). A value
of 0x0f results in 15 cycles and so on. Note that software can always cause an update of the slave-delay
line using the SLV_FORCE_UPDATE register. Note that the slave delay line will also update automatically
when the reference DLL transitions to a locked state (from an un-locked state).
Reserved
When SLV_OVERRIDE=1 This field is used to select 1 of 64 physical taps manually. A value of 0 selects
tap 1, and a value of 0x3f selects tap 64.
Set this bit to 1 to Enable manual override for slave delay chain using SLV_OVERRIDE_VAL; to set 0 to
disable manual override. This feature does not require the DLL to tbe enabled using the ENABLE bit. In fact
to reduce power, if SLV_OVERRIDE is used, it is recommended to disable the DLL with ENABLE=0
Reserved
Setting this bit to 1, forces the slave delay line not update
29
13
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
0
0
HW_SSP_DLL_CTRL field descriptions
8001_0000h base + F0h offset = 8001_00F0h
27
11
0
0
26
10
0
0
25
0
0
9
SLV_UPDATE_INT
RSVD0
24
0
0
8
Description
23
0
0
7
22
0
0
6
SLV_DLY_TARGET
Chapter 17 Synchronous Serial Ports (SSP)
21
0
5
0
20
0
4
0
19
0
0
3
18
0
0
2
RSVD1
17
0
0
1
1345
16
0
0
0