MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1315

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

17.5.1 SPI DMA Mode
The SPI bus is inherently a full-duplex bidirectional interface. However, as most applications
only require half-duplex data transmission, the i.MX28 has a single DMA channel for the
SSP. It can be configured for either transmit or receive. In DMA receive mode, the SPI
continuously repeats the word written to its data register. In DMA transmit mode, the SPI
ignores the incoming data.
17.5.2 Motorola SPI Frame Format
The Motorola SPI interface is a four-wire interface where the SSn signal behaves as a slave
select. The main feature of the Motorola SPI format is that the inactive state and phase of
SSP_SCK signal are programmable through the polarity and phase bits within the
HW_SSP_CTRL1.
17.5.2.1 Clock Polarity
17.5.2.2 Clock Phase
The phase control bit selects the clock edge that captures data and allows it to change state.
It has the most impact on the first bit transmitted, by either allowing or not allowing a clock
transition before the first data-capture edge.
17.5.3 Motorola SPI Format with Polarity=0, Phase=0
Single and continuous transmission signal sequences for Motorola SPI format with
POLARITY=0, PHASE=0 are shown in
Freescale Semiconductor, Inc.
• When the clock polarity control bit is low, it produces a steady-state low value on the
• When the clock polarity control bit is high, a steady-state high value is placed on the
• When the phase control bit is low, data is captured on the first clock-edge transition.
• When the clock phase control bit is high, data is captured on the second clock-edge
SSP_SCK pin.
SSP_SCK pin when data is not being transferred.
transition.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Figure 17-2
and
Chapter 17 Synchronous Serial Ports (SSP)
Figure
17-3.
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