MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1822

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MCIMX286CVM4B

Manufacturer Part Number
MCIMX286CVM4B
Description
IC MPU I.MX286 289MAPBGA
Manufacturer
Freescale Semiconductor
Series
i.MX28r

Specifications of MCIMX286CVM4B

Core Processor
ARM9
Core Size
32-Bit
Speed
454MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
Peripherals
DMA, I²S, LCD, POR, PWM, WDT
Program Memory Size
128KB (32K x 32)
Program Memory Type
Mask ROM
Ram Size
32K x 32
Voltage - Supply (vcc/vdd)
1.25 V ~ 5.25 V
Data Converters
A/D 17x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
289-LFBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Compliant
Ipv4 and Ipv6 Priority Look Up
If a Broadcast frame is received, the switch Hardware sends the received frame to all output
ports, except the one from which it was received (Flooding).
29.4.9.2 Forced Forwarding
The MAC address lookup result can be overwritten using the forced forwarding configuration
available in the register FORCE_FWD_P0. This feature is available only for frames coming
from the local port (Port 0).
When forced forwarding is enabled for a frame, the frame will be forwarded to the forced
destination port(s), ignoring any results from the MAC destination address lookup. Forced
forwarding only replaces the mac lookup function, all other filtering functions (for example,
VLAN verification) act as normal.
29.4.9.3 Learning
The Switch Hardware extracts the source MAC address of each frame received on each of
the switch ports and provides it, through the registers
the Switch Firmware which implements the learning task. The register
indicates availability of learning data.
Learning Interface
The interface implements a FIFO buffer that stores up to 32 words of 32-bit each.
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• The Switch engine sends the received frame to all ports except the port on which
it was received (Flooding).
Flooding and additional frame filtering can be controlled, for
example, to avoid the duplication of critical information to
unwanted destinations, with the mechanism described in Section
5.10.3 page 41.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Note
LRN_REC_0
and LRN_REC_1, to
Freescale Semiconductor, Inc.
LRN_STATUS

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