MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 1171

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

14.8.71 DRAM Control Register 76 (HW_DRAM_CTL76)
This is a DRAM configuration register.
Address:
Re-
14.8.72 DRAM Control Register 77 (HW_DRAM_CTL77)
This is a DRAM configuration register.
Address:
Re-
Freescale Semiconductor, Inc.
set
set
Bit
Bit
W
W
R
R
PHY_CTRL_
REG_1_1
31
31
0
0
Field
Field
31 0
30
30
0
0
29
29
0
0
HW_DRAM_CTL76
HW_DRAM_CTL77
28
28
0
0
Bits [10:8] = Gate Error Delay. Allows the user to adjust the length of time from the dfi_rddata_en assertion
to the maximum time in which all of the data should have been returned. If the data is not returned in the
time expected by the MC, an error condition may occur. This field default value is based on the delay
information provided at configuration.
Bits [5:4] = Adjusts the closing of the gate. This field default value is based on the delay information provided
at configuration.
Bits [2:0] = Coarse adjust of gate open time. This value is the number of cycles to delay the dfi_rddata_en
signal prior to opening the gate in full cycle increments. Decreasing this value pulls the gate earlier in time.
This field, along with the phy_ctrl_reg_0_X [16] bit should be programmed such that the gate signal lands
in the valid DQS gate window.
Controls pad termination and loopback for data slice 1.
There is a separate phy_ctrl_reg_1_X parameter for each of the slices of data sent on the DFI data bus.
The definition of phy_ctrl_reg_1_X parameter is same for data slice 0~3.
27
27
0
0
26
26
0
0
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
25
25
0
0
HW_DRAM_CTL75 field descriptions (continued)
24
24
0
0
23
23
0
0
HW_DRAM_CTL76 field descriptions
800E_0000h base + 130h offset = 800E_0130h
800E_0000h base + 134h offset = 800E_0134h
22
22
0
0
21
21
0
0
20
20
0
0
19
19
0
0
PHY_CTRL_REG_1_1
PHY_CTRL_REG_1_2
18
18
0
0
17
17
0
0
16
16
0
0
15
15
0
0
Description
Description
14
14
0
0
13
13
0
0
12
12
0
0
Chapter 14 External Memory Interface (EMI)
11
11
0
0
10
10
0
0
0
0
9
9
0
0
8
8
0
0
7
7
0
0
6
6
0
0
5
5
0
0
4
4
3
0
3
0
0
0
2
2
0
0
1
1
1171
0
0
0
0