MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 844

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Clock Structure
system. The diagram that follows depicts all clock domains and how they are connected
within the CLKCTRL module. This should provide a reference for how clocks are generated
within the i.MX28 system.
10.2.1 Table of System Clocks
The following table summarizes the clocks produced by the clock control module.
844
ref_enet_pll
clk_h_flex-
ref_hsadc
can0_ipg
ref_gpmi
ref_xtal
ref_cpu
ref_emi
ref_io0
ref_io1
ref_pix
NAME
ref_pll
clk_p
clk_h
REFERENCE
xtal_24m/
ring_24m
/ref_cpu
ref_xtal
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
PLL0
PLL2
clk_p
clk_h
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
VIDE/FREQ
10/6 bits
9 phase
9 phase
9 phase
9 phase
9 phase
9 phase
9 phase
Divided clock domains referenced from PLL or Xtal clock.
5 bits
DI-
1
1
1
1
Table 10-1. System Clocks
This is the muxed select between the internal ring oscillator and the external
crystal.
The 9 phase fractional divider output used as the reference for the CPU clock
divider.
The 9 phase fractional divider output used as the reference for the EMI clock di-
vider.
The 9 phase fractional divider output used as the reference for the SSP0/SSP1
clock dividers.
The 9 phase fractional divider output used as the reference for the SSP2/SSP3
clock divider.
The 9 phase fractional divider output used as the reference for the LCDIF clock
divider.
The 9 phase fractional divider output used as the reference for the HSADC clock
divider.
The 9 phase fractional divider output used as the reference for the GPMI clock
divider.
This is the raw PLL output used as the reference for the SAIF0 and SAIF1 clock
divider.
This is the raw PLL output used as the reference for the ENET clock divider.
ARM core clock.
AHB/APBH clock domain. clk_h is a gated branch of the clk_p domain.
Flexcan0 Message Buffer Management (MBM) clock whose clock gating is con-
trolled by hw_clkctrl_flexcan register.
DESCRIPTION
Reference Clocks.
Freescale Semiconductor, Inc.