MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2305

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

HW_LRADC_DEBUG1_CLR: 0x128
HW_LRADC_DEBUG1_TOG: 0x12C
The LRADC DEBUG1 register provides, read-only diagnostic information and control over
the test modes of LRADC channels 5, 6 and 7. This is only used in debugging the LRADC.
EXAMPLE
BW_LRADC_DEBUG1_TESTMODE(BV_LRADC_DEBUG1_TESTMODE__TEST);
Address:
Freescale Semiconductor, Inc.
Reset
Reset
TESTMODE_
TESTMODE6
TESTMODE5
REQUEST
Bit
Bit
W
W
RSRVD3
RSRVD2
RSRVD1
R
R
COUNT
31 24
23 16
15 13
Field
12 8
7 3
2
1
31
15
0
0
RSRVD2
HW_LRADC_DEBUG1
30
14
0
0
Reserved
LRADC internal request register.
Reserved
When in test mode, the value in this register will be loaded in to a counter which is decremented upon each
Channel 7 conversion. When that counter decrements to zero, the HW_LRADC_CH7.TESTMODE_TOGGLE
field will be toggled, indicating that the conversion value of interest is available in the
HW_LRADC_CH7.VALUE bit field.
Reserved
Force dummy conversion cycles on channel 6 during test mode.
0x0
0x1
Force dummy conversion cycles on channel 5 during test mode.
0x0
0x1
29
13
0
0
NORMAL — Normal operation.
TEST — Put it in test mode, i.e. continuously sample channel 6.
NORMAL — Normal operation.
TEST — Put it in test mode, i.e. continuously sample channel 5.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
28
12
RSRVD3
0
0
HW_LRADC_DEBUG1 field descriptions
TESTMODE_COUNT
27
11
0
0
8005_0000h base + 120h offset = 8005_0120h
26
10
0
0
Chapter 38 Low-Resolution ADC (LRADC) and Touch-Screen Interface
25
0
0
9
24
0
0
8
Description
23
0
0
7
22
0
0
6
RSRVD1
21
0
5
0
REQUEST
20
0
4
0
19
0
0
3
18
0
0
2
17
0
0
1
2305
16
0
0
0