MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 994

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

NAND Boot Mode
There are eight data blocks of 512 bytes, each in a page of a 4K page sized NAND. The
values of EccB0 and EccBN should be such that above calculation should not result in a
value greater than the size of a page in a 4K page NAND.
12.12.2.2 Metadata
The number of bytes used for metadata are specified in FCB. Metadata for BCH encoded
pages will be placed at the beginning of a page. ROM only cares about the first byte of
metadata to swap it with bad block marker byte in page data after each page read. It is
therefore important to have at least one byte for metadata bytes field in FCB data structure.
12.12.2.3 efuses/OTP bits used by ROM NAND Driver
994
ROM1:2..0
ROM1:7..4
ROM1:11..8
ROM1:27..20
ROM1:30
ROM4:3..0
ROM4:7..4
Register
NUMBER_OF_NANDS
BOOT_SEARCH_STRIDE
BOOT_SEARCH_COUNT
ENABLE_NAND_CE_RDY_PULLUPS
DISABLE_SECONDARY_BOOT
NAND_ROW_ADDRESS_BYTES
NAND_COLUMN_ADDRESS_BYTES
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
Name
Table 12-33. eFuses
Three bits used for number of NANDs on the device. If left unblown,
boot ROM will default to 1 device. It is important to program these
bits to exact number of NANDs in the system, using this information
ROM will enable internal pullups. The boot may fail if this field is in-
correctly programmed. Max number of NAND devices allowed in
MX28 is 8, but ROM only supports boot from NAND0.
Four bits for boot search stride. Boot ROM defaults it to 1. ROM
multiplies this number with 64 to get search stride in pages. Typically,
this should be left 0 or 1 for NAND devices with number of pages per
block as 64. For 128 pages per block, it is recommended to program
these bits to a value of 2 in order for each BCB to be placed in a new
block.
Four bits for boot search count. If not programmed, boot ROM will
default to 2. This value is raised to the power of 2 to get actual boot
search count. Boot search count will tell ROM how many times a BCB
is duplicated in a search area.
Eight bits to enable internal pullups on CE and RDY pins. Bit 20 is
used to enable pullups on NAND0,
Bit 21 is used to enable pullups on NAND1,...
...
Bit 27 is used to enable pullups on NAND7.
One bit to disable redundant boot. If this bit is programmed to 1, ROM
will not try to boot from the secondary image if the primary image
failed to boot.
Four bits for number of row address bytes. If not programmed, ROM
will default to 3 bytes for row (page) address.
Four bits for number of column address bytes. If not programmed,
ROM will default to 2 column address bytes.
Description
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