MCIMX286CVM4B Freescale Semiconductor, MCIMX286CVM4B Datasheet - Page 2318

• Manufacturer Part Number: MCIMX286CVM4B
• Description: IC MPU I.MX286 289MAPBGA
• Manufacturer: Freescale Semiconductor
• Series: i.MX28r

Specifications of MCIMX286CVM4B

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 454MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, MMC, SmartCard, SPI, SSI, UART/USART, USB OTG
• Peripherals: DMA, I²S, LCD, POR, PWM, WDT
• Program Memory Size: 128KB (32K x 32)
• Program Memory Type: Mask ROM
• Ram Size: 32K x 32
• Voltage - Supply (vcc/vdd): 1.25 V ~ 5.25 V
• Data Converters: A/D 17x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 289-LFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Compliant

Background
int i, iMode = 0, iRun = 0;
//
39.3 Background
The i.MX28 SOC is built on a 32-bit architecture using an ARM926 core. All hardware
blocks are controlled and accessed through 32-bit wide registers. The design of these registers
is maintained in a database that is part of the overall chip design. As part of the chip build
process, a set of C include files are generated from the register descriptions. These include
files provide a consistent set of C defines and macros that should be used to access the
hardware registers.
The i.MX28 SOC has a complex architecture that uses multiple buses to segment I/O traffic
and clock domains. To facilitate low power consumption, clocks are set to just meet
application demands. In general, the I/O buses and associated hardware blocks run at speeds
much slower than the CPU. As a result, reading a hardware register incurs a potentially
large number of wait cycles, as the CPU must wait for the register data to travel multiple
buses and bridges. The SOC does provide write buffering, meaning the CPU does not wait
for register write transactions to complete. From the CPU perspective, register writes occur
much faster than reads.
Most of the 32-bit registers are subdivided into smaller functional fields. These bit fields
can be any number of bits wide and are usually packed. Thus, most fields do not align on
byte or half-word boundaries.
A common operation is to update one field without disturbing the contents of the remaining
fields in the register. Normally, this requires a read-modify-write (RMW) operation, where
the CPU reads the register, modifies the target field, then writes the results back to the
register. As already noted, this is an expensive operation in terms of CPU cycles, because
of the initial register read.
To address this issue, most hardware registers are implemented as a set, including registers
that can be used to either set, clear, or toggle (SCT) individual bits of the primary register.
When writing to an SCT register, all bits set to 1 perform the associated operation on the
primary register, while all bits set to 0 are not affected. The SCT registers always read back
0, and should be considered write-only. The SCT registers are not implemented if the primary
register is read-only.
With this architecture, it is possible to update one or more fields using only register writes.
First, all bits of the target fields are cleared by a write to the associated clear register, then
the desired value of the target fields is written to the set register. This sequence of two writes
is referred to as a clear-set (CS) operation.
i.MX28 Applications Processor Reference Manual, Rev. 1, 2010
2318
Freescale Semiconductor, Inc.